ARM Cortex-M0 DesignStart Processor and v6-M …

1 1 ARM Cortex-M0 DesignStartProcessor and v6-M ArchitectureJoe BungoARM University Program Manager Americas/EuropeR&D Division23 Agenda Introduction to ARM LtdCortex-M0 DesignStart ProcessorARM v6-M Programmers ModelARM v6-M Exception HandlingARM v6-M Instruction Set OverviewPipelineM0_DS EDK Example System4 ARM LtdARM founded in November 1990 Advanced RISC MachinesCompany headquarters in Cambridge, UK Processor design centers in Cambridge, Austin, and Sophia Antipolis Sales, support, and engineering offices all over the worldBest known for its range of RISC Processor cores designs Other products fabric IP, software tools, models, cell libraries - to help partners develop and ship ARM-based SoCsARM does notmanufacture siliconMore information about ARM and our offices on our web site: Worldwide6 ARM s ActivitiesmemorymemorySoCSoCProcessorsSy stem Level IP.

2 Data EnginesFabric3D GraphicsPhysical IPSoftware IPDevelopment ToolsConnected Community7 ARM Connected Community 800+8 Huge Range of ApplicationsEnergy Efficient AppliancesIR Fire Detector Intelligent Vending Tele-parking Utility Meters Exercise MachinesIntelligent toysEquipment Adopting 32-bit ARM Microcontrollers9 Huge Opportunity For ARM Technology199820132020billion30+billion3 0+30+cores to date100+billion100+100+billioncores accumulated after next 9 yrs10 ARM cortex -Afamily: Applications processors for feature-rich OS and 3rdparty applications ARM cortex -Rfamily: Embedded processors for real-time signal processing, control applications ARM cortex -Mfamily: Microcontroller-oriented processors for MCU, ASSP, and SoC applicationsARM cortex Advanced Processors<12k + Performance**Represents attainable speeds in 130, 90, 65, or 45nm processesCortex-M0 cortex -M3 ARM7 ARM926 ARM1026 ARM1136 ARM1176 cortex -A8 cortex -A9 Dual-coreMax Freq (MHz)5015018447054061075011002000 Min Power (mW/MHz) Frequency (Mhz)12 AgendaIntroduction to ARM Ltd Cortex-M0 DesignStart ProcessorARM v6-M Programmers ModelARM v6-M Exception HandlingARM v6-M Instruction Set OverviewPipelineM0_DS EDK Example System13 cortex familyCortex-A8 Architecture v7A MMU AXI VFP & NEON supportCortex-R4 Architecture v7R MPU (optional)

3 AXI Dual IssueCortex-M3 Architecture v7M MPU (optional) AHB Lite & APB14 Cortex-M0 DesignStart Processor15 ARM Cortex-M0 Processor featuresFull productoptions M0_DS implementationVerilog core Flattened and ObfuscatedAMBA AHB-lite interface ARMv6-M instruction set architecture NVIC Interrupt controller Interrupt line configurations1 to 3216 onlyDebug (SWD, JTAG) option Up to 4 breakpoints, 2 watchpoints Low power optimisations (ACG) Multiple power domain support with WIC Fast multiplier (1 cycle) option System timer Area (gates)12k 25k16 KCortex-M0 DesignStart Differences16 AgendaIntroduction to ARM LtdCortex-M0 DesignStart Processor ARM v6-M Programmers ModelARM v6-M Exception HandlingARM v6-M Instruction Set OverviewPipelineBasic System Design17v6-M Data Types ARM v6-M is a 32-bit architecture.

4 When used in relation to the ARM: Bytemeans 8 bits Halfwordmeans 16 bits (two bytes) Wordmeans 32 bits (four bytes) Doublewordmeans 64 bits (eight bytes)18 Cortex-M0 Programmers Model The Cortex-M0 is designed to be programmed fully in C No need to write assembly code Full Thumb technology, and subset of Thumb2 16-bit and 32-bit instructions Set of Processor core and memory-mapped registers are provided Forwards compatible with other M-profile processors In-order execution of instructions All instructions are treated as restartable Including LDM/STM19 cortex -M Differences Fully programmable in C Stack-based exception model Only two Processor modes Thread Mode for User tasks Handler Mode for OS tasks and exceptions Vector table contains addresses20 Cortex-M0 Memory Map Device 511 MBPrivate Peripheral Bus 1 MBExternal Device 1 GBExternal RAM 1 GBPeripheral 500 MBSRAM 500 MBCode

5 500MB0x0000 00000x2000 00000x4000 00000x6000 00000xA000 00000xE000 00000xE010 0000 Executable region for program code and data(vector table is fixed at address 0x0000 0000)Data Memory (code can also be placed here)External Peripherals (XN)External MemoryExternal Peripherals (XN)Core Memory Mapped Register Space, NVIC (XN) XN execute never21 Cortex-M0 Register Set All registers are 32 bits wide 13 general purpose registers Registers r0 r7 (Low registers) Registers r8 r12 (High registers) 3 registers with special meaning/usage Stack Pointer (SP) r13 Link Register (LR) r14 Program Counter (PC) r15 Special-purpose registers xPSR shows a composite of the content of APSR, IPSR, EPSRP rocess(Handler Mode)r8r9r10r11r12splrr15 (pc)xPSRr0r1r2r3r4r5r6r7 Main (Thread Mode)sp22 Register Usager8r9r10r11r12r13/spr14/lrr15/pcr0r1 r2r3r4r5r6r7 Register variablesMust be preservedArguments into functionResult(s) from functionotherwise corruptible(Additional parameters passed on stack)Scratch register(corruptible)Stack PointerLink RegisterProgram CounterThe compiler has a set of rules known as a Procedure Call Standard that determine how to pass parameters to a function (see AAPCS)

6 CPSR flags may be corrupted by function callAssembler code which links with compiled code must follow the AAPCS at external interfacesThe AAPCS is part of the ABI for the ARM ArchitectureRegister- r14 can be used as a temporary once value stacked23 APSR - Application Program Status Register Contains the Negative, Zero, Carry and OVerflow flags from the ALU IPSR Interrupt Program Status Register EPSR Execution Program Status Register Thumb code is executed01234567891011121314151617181920 2122232425262728293031 The PSR Registers0123456789101112131415161718192 0212223242526272829303101234567891011121 3141516171819202122232425262728293031 NZCVE xceptionNumberT24 xPSR Composite register of APSR.

7 IPSR and EPSR IEPSR Composite register of IPSR and EPSR012345678910111213141516171819202122 232425262728293031 The PSR Composite RegistersNZCVE xceptionNumberT0123456789101112131415161 71819202122232425262728293031 ExceptionNumberT25 Processor Mode Usage Processor mode may change when exceptions occur Thread Mode is entered on Reset Handler Mode is entered on all other exceptions Both modes have full access to all system resources No concept of privilege. Mechanism exists but has no meaning to M0 ARM Cortex-M0 ProcessorThreadModeApplication CodeHandlerModeException CodeSVCPendSVFaultsSysTickExceptionRetur nResetInterruptsFaults26 AgendaIntroduction to ARM LtdCortex-M0 DesignStart ProcessorARM v6-M Programmers Model ARM v6-M Exception HandlingARM v6-M Instruction Set OverviewPipelineM0_DS EDK Example System27 Supported ExceptionsResetProcessor reset input is assertedHardFaultAny type of fault Bus fault or undefined instructionNMINon-Maskable Interrupt occurredIRQsIRQ Interrupts occurredPendSVSoftware generated interruptSVCallExecution of a SVC instructionSysTickInternal system timer caused interruptUsing Handler ModeUsing Thread Mode

8 Seven exception types are supported28 Exception Properties Each exception has associated propertiesException number Identification for the exceptionVector address Exception entry point in memoryPriority level Determines the order in which multiple pending exceptions are handled29 Vector TableInterrupt #31 Handler #0 Handler VectorSysTick Handler VectorPendSV Handler VectorreservedSVCall Handler VectorreservedHardFault Handler VectorNMI Handler VectorReset Handler VectorInitial value of MSP0xBF-0x400x3C0x38-0x2C-0x0C0x080x040x 00 Vector table contains the following information Handler vector addresses Initial value of the Main Stack Pointer (MSP)30 Exception Numbers & Vector Addresses Exception number is used to calculate the vector address Exception number defines the word offset from 0x0 Exception numbers which are not shown are reservedNameException NumberVector AddressInterrupts #0 - #31 (N interrupts)16 to 16 + N0x40 0xBFSysTick (SysTick Extension)150x3 CPendSV140x38 SVCall110x2 CHardFault30x0 CNon Maskable Interrupt (NMI)20x08 Reset10x0431 Exception Entry Overview The Exception Entry sequence is as follows Perform Stack Push (R0-R3, R12, R14, PC (return address), and xPSR) Select Handler Mode Update registers Set LR to EXC_RETURN (architectural value)

9 Generated automatically when exception accepted Special value that indicates exception return vs. subroutine return Also indicates mode to return to Set IPSR<5:0> to the Exception Number Set bit Set PC to the vector address32 Vector Table UsageHandler VectorHandler In the case of an exception, the core Reads the vector handler address for the exception from the vector table Branches to the handlerHandler Vectorpoints to theHandler code33 Exception Return Exception returns can be accomplished using the following instructions POP which includes loading the PC BX with any register Usually LR is used Exception return is performed in the following steps LR value (EXC_RETURN) is loaded into the PC to signal an exception return Since no special instruction for exception return needed, handlers can be written as normal C functions Change mode & stack Dependent on EXC_RETURN Stack Pop of AAPCS registers is performed Includes load of return address into the PC34 Reset Behavior1.

10 A reset exception occurs (Reset input was asserted)2. Load MSP (Main Stack Pointer) register initial value from address 0x003. Load reset handler vector address from address 0x044. Reset handler executes in Thread Mode5. Optional: Reset handler branches to the main program0x040x001 Reset HandlerInitial value of MSPR eset Handler Vectorr13 (MSP)243 Main535 Interrupt Handling One Non-Maskable Interrupt (INTNMI) supported 16 prioritizable interrupts supported Interrupts can be masked Implementation option selects number of interrupts supported Nested Vectored Interrupt Controller (NVIC) is tightly coupled with Processor core Interrupt inputs are active HIGH Tail-chaining supportedCortex-M0 Processor CoreNMINVICC ortex-M0 16 ControlNVIC0xE000ED000xE000E1000xE000E10 0 ISERICER0xE000E1800xE000E200 ISPR0xE000E280 ICPR0xE000E400 IPR[0]0xE000E41 CIPR[7]System Control Block0xE000ED90 System Control SpaceICSR0xE000ED0437 Interrupt Enable Registers ISER - Interrupt Set-Enable Register Used to enable interrupts ICER - Interrupt Clear-Enable Regist