ARM Instruction Set - 國立臺灣大學

1 ARM Instruction SetComputer Organization and Assembly Languages pgzyggYung-Yu Chuang with slides by Peng-Sheng ChenIntroduction The ARM processor is easy to program at the assembly level (It is a RISC)assembly level. (It is a RISC) We will learn ARM assembly programming at the ll d it il tuser level and run it on a programmer model The state of an ARM system is determined by the content of visible registers and memorythe content of visible registers and memory. A user-mode program can see 15 32-bit general- it (R0R14) t purpose registers (R0-R14), program counter (PC) and CPSR. Instruction set defines the operations that can change the system Memory is a linear array of bytes addressed from 0 to 000x00000000bytes addressed from 0 to 232-1Wd hlfd b t10200x000000010x00000002 Word, half-word, byte Little-endian30FF0x000000030x00000004 FFFF0x000000040x000000050x00000006000x00 0000060 FFFFFFFD00000xFFFFFFFE0xFFFFFFFD0xFFFFFF FFByte ordering Big EndianLeast significant byte has 000x00000000 Least significant byte has highest addressWord address 0x00000000 0010200x000000000x000000010 00000002 Value: 00102030 Little Endian2030FF0x000000020x00000003 Least significant byte has lowest addressFFFFFF0x000000040x00000005 Word address 0x00000000 Value.

2 30201000FF000x0000000600000xFFFFFFFE0xFF FFFFFD000xFFFFFFFF0xFFFFFFFEARM programmer model000x0000000010200x000000010x0000000 2R0R1R2R330FF0x000000020x000000030 00000004R4R5R6R7R8R9R10R11 FFFFFF0x000000040x00000005R8R9R10R11R12R 13R14 PCFF000x000000060000000xFFFFFFFE0xFFFFFF FD000xFFFFFFFF0 Instruction setARM instructions are all 32bit long are all 32-bit long (except for Thumb mode) Thumb mode). There are 232possible machine possible machine instructions . Fortunately they Fortunately, they are of ARM Instruction set Load-store architecture3dd ii 3-address instructions Conditional execution of every Instruction Possible to load/store multiple registers at once Possible to combine shift and ALU operations in a single instructiona single instructionInstruction set Data processingD ( ) Data movement (memory access) Flow controlData processing They are move, arithmetic, logical, comparison and multiply instructionsand multiply instructions .

3 Most data processing instructions can process f th i d i th bl hift one of their operands using the barrel shifter. General rules: All operands are 32-bit, coming from registers or literals. The result, if any, is 32-bit and placed in a register (with the ti f l g lti l exception for long multiply which produces a 64-bit result)3address format 3-address formatInstruction setMOV<cc> <S> Rd, <operands>MOVCS R0, R1 @ if carry is set@ then R0:=R1 MOVS R0, #0 @ R0:=0@ Z=1, N=0,@ C, V unaffectedConditional execution Almost all ARM instructions have a condition field which allows it to be executed field which allows it to be executed R0, R1 Register movementimmediate,register,shift MOV R0, R2 @ R0 = R202@0 2 MVN R0, R2@ R0 = ~R2 tdmove negatedAddressing modes Register operandsADDR0R1R2 ADD R0, R1, R2 Immediate operandsa literal; most can be represented ADDR3R3#1 @R3:=R3+1a literal.

4 Most can be represented by ( )x22n0<n<12 ADD R3, R3, #1 @ R3:=R3+1 AND R8, R7, #0xff @ R8=R7[7:0]a hexadecimal literalThis is assembler dependent syntaxThis is assembler dependent register operands One operand to ALU is routed through the Barrel routed through the Barrel shifter. Thus, the operand can be modified before it can be modified before it is used. Useful for fast multipliation and dealing pgwith lists, table and other complex data structure. (similar to the displacement addressing d i CSC Some instructions ( MUL CLZ QADD) do mode in CISC.)MUL, CLZ, QADD) do not read barrel register operandsLogical shift leftCC0registerMOV R0, R2, LSL #2@ R0:=R2<<2@ R2 unchangedgExample: 0011 0000 Before R2=0x00000030 Before R2 0x00000030 After R0=0x000000C0R2=0x00000030R2=0x00000030 Logical shift rightC0registerMOV R0, R2, LSR #2 @ R0:=R2>>2@ R2 unchangedgExample: 0011 0000 Before R2=0x00000030 Before R2 0x00000030 After R0=0x0000000CR2=0x00000030R2=0x00000030 Arithmetic shift rightMSBregisterCMOV R0, R2, ASR #2 @ R0:=R2>>2@ R2 unchangedgExample: 1010 0011 0000 Before R2=0xA0000030 Before R2 0xA0000030 After R0=0xE800000CR2=0xA0000030R2=0xA0000030 Rotate rightregisterMOV R0, R2, ROR #2 @ R0:=R2 rotate@ R2 unchangedgExample: 0011 0001 Before R2=0x00000031 Before R2 0x00000031 After R0=0x4000000CR2=0x00000031R2=0x00000031 Rotate right extendedCregisterCCMOV R0, R2, RRX@ R0.

5 =R2 rotate@ R2 unchangedgExample: 0011 0001 Before R2=0x00000031, C=1 Before R2 0x00000031, C1 After R0=0x80000018, C=1R2=0x00000031R2=0x00000031 Shifted register operandsShifted register operandsShifted register operands It is possible to use a register to specify the number of bits to be shifted; only the bottom 8 number of bits to be shifted; only the bottom 8 bits of the register are significant.@idllti@ array index calculationADD R0, R1, R2, LSL R3@ R0:=R1+R2*2R3@ fast multiply R2=35xR0 ADD R0, R0, R0, LSL #2 @ R0 =5xR0 RSB R2, R0, R0, LSL #3 @ R2 =7xR0 MultiplicationMOV R1, #35 MULR2R0R1 MUL R2, R0, R1or0 0 0 #2@0 50 ADD R0, R0, R0, LSL #2 @ R0 =5xR0 RSB R2, R0, R0, LSL #3 @ R2 =7xR0 Shifted register operandsEncoding data processing instructionscond0 0operand 2#opcodeSRnRd3128 27 26 25 2421 20 1916 1512 110destination registerfirst operand registerset condition codesset condition codesarithmetic/logic function8bit idi t25118 70#t8-bit immediate1#rot117 6 5 4 30immediate alignmentRm#shift025Sh0immediate shift lengthfRm0118765430Rs10 Shshift typesecond operand registerRmRs10 Shregister shift lengthArithmetic Add and subtractionArithmetic ADD R0, R1, R2 @ R0 = R1+R2 ADCR0R1R2@R0 R1R2C ADC R0, R1, R2@ R0 = R1+R2+C SUB R0, R1, R2 @ R0 = R1-R2 SBC R0, R1.

6 R2 @ R0 = R1-R2-!C RSB R0, R1, R2@R0=R2-R1 RSB R0, R1, R2@ R0 R2R1 RSC R0, R1, R2 @ R0 = R2-R1-!C0127128130127-128-12551281270-53 -5=3+(-5) sum<=255 C=0 borrow25512812705-3=5+(-3) sum > 255 C=1 no borrowArithmeticArithmeticSetting the condition codes Any data processing Instruction can set the condition codes if the programmers wish it tocondition codes if the programmers wish it to64-bit additionR1R0 ADDSR2, R2, R0 ADC R3 R3 R1R3R2+ADC R3, R3, R1R3R2 LogicalLogical AND R0, R1, R2 @ R0 = R1 and R2 ORRR0R1R2@R0 R1 R2 ORR R0, R1, R2@ R0 = R1 or R2 EOR R0, R1, R2 @ R0 = R1 xor R2 BIC R0, R1, R2 @ R0 = R1 and (~R2)bit clear: R2is a mask identifying which bits of R1will be cleared to zeroR1=0x11111111 R2=0x01100101 BIC R0, R1, R2R0=0x10011010R0=0x10011010 LogicalComparison These instructions do not generate a result, but set condition code bits (N Z C V) in CPSR set condition code bits (N, Z, C, V) in CPSR.

7 Often, a branch operation follows to change the program flowprogram CMP R1 R2@ set cc on R1-R2compare CMP R1, R2@ set cc on R1-R2 CMN R1 R2@ set cc on R1+R2compare negated CMN R1, R2@ set cc on R1+R2 TST R1 R2@ set cc on R1 and R2bit test TST R1, R2@ set cc on R1 and R2 TEQ R1 R2@ t R1 R2test equal TEQ R1, R2@ set cc on R1 xor R2 ComparisonMultiplicationMultiplication MUL R0, R1, R2 @ R0 = (R1xR2)[31:0] Features:Sd d t b idit Second operand can t be immediate The result register must be different from the first operand Cycles depends on core typeypyp If S bit is set, C flag is meaningless See the reference manual (4 1 33) See the reference manual ( )Multiplication Multiply-accumulate (2D array indexing)MLAR4R3R2R1@R4=R3xR2+R1 MLA R4, R3, R2, R1 @ R4 = R3xR2+R1M lti l ith t t ft b Multiply with a constant can often be more efficiently implemented using shifted register operand operand MOV R1, #35 MULR2R0R1 MUL R2, R0, R1orADD R0, R0, R0, LSL #2 @ R0 =5xR0 RSB R2, R0, R0, LSL #3 @ R2 =7xR0 MultiplicationMultiplicationFlow control instructions Determine the Instruction to be executed nextpc-relative offset within 32 MBFlow control instructions Branch.

8 Conditional branchesMOV R0, #0 MOV R0, #0loop: ..ADD R0 R0 #1 ADD R0, R0, #1 CMP R0, #10 BNEloopBranch conditionsBranchesBranch and link BLinstruction saves the return address to R14(lr)(lr)BL sub @ call subCMP R1, #5 @ return to hereMOVEQ R1, # : .. @ sub entry PC, LR @ return Branch and linkBL sub1 @ call stack to save/restore the return address and registerssub1:STMFD R13!, {R0-R2,R14}BL R13!, {R0-R2,PC},{,}sub2:sub2:..MOV PC LRMOV PC, LRConditional executionCMP R0, #5 BEQ b pass @ if (R0! 5) {BEQ bypass @ if (R0!=5) {ADD R1, R1, R0 @ R1=R1+R0-R2 SUB R1, R1, R2 @ }bypass: ..CMP R0, #5smaller and faster,ADDNE R1, R1, R0 SUBNE R1 R1 R2 SUBNE R1, R1, R2 Rule of thumb: if the conditional sequence is three instructionsqor less, it is better to use conditional execution than a executionif ((R0==R1) && (R2==R3)) R4++CMP R0, R1 BNE skipBNE skipCMP R2, R3 BNE skipBNE skipADD R4, R4, #1skip:skip.}

9 CMP R0 R1 CMP R0, R1 CMPEQ R2, R3 ADDEQ R4 R4 #1 ADDEQ R4, R4, #1 Conditional executionCMP R0, R1 BNE skipFDEFDEBNE skipCMP R2, R3 BNE skipFDEFDEFDEBNE skipADD R4, R4, #1 FDEFDECMP R0 R1 FDECMP R0, R1 CMPEQ R2, R3 ADDEQ R4 R4 #1 FDEFDEFDEADDEQ R4, R4, #1 FDEData transfer instructions Move data between registers and memoryTh b i f Three basic forms Single register load/store Multiple register load/store Single register swap: SWP(B),atomic Single register swap: SWP(B),atomic Instruction for semaphoreSingle register load/storeSingle register load/storeNo STRSB/STRSH since STRB/STRH stores both id/id signed/unsigned onesSingle register load/store The data items can be a 8-bit byte, 16-bit half-word or 32bit word Addresses must be word or 32-bit word. Addresses must be boundary aligned. ( 4 s multiple for LDR/STR)LDR/STR)LDR R0, [R1]@ R0 := mem32[R1]STR R0, [R1] @ mem32[R1] := R0 LDR, LDRH, LDRB for 32, 16, 8 bits,,,,STR, STRH, STRB for 32, 16, 8 bitsAddressing modes Memory is addressed by a register and an [R1]@ [R1]LDR R0, [R1]@ mem[R1] Three ways to specify offsets: ImmediateLDR R0, [R1, #4] @ mem[R1+4]Ri RegisterLDR R0, [R1, R2] @ mem[R1+R2]Scaled register @ [R1+4*R2] Scaled register @ mem[R1+4*R2]LDR R0, [R1, R2, LSL #2]Addressing modes Pre-index addressing (LDR R0, [R1, #4])ih i b kwithout a writeback Auto-indexing addressing (LDR R0, [R1, #4]!

10 Pre-index with writebackcalculation before accessing with a writeback calculation before accessing with a writeback Post-index addressing (LDR R0, [R1], #4)l l ti ft i ith it b k calculation after accessing with a writeback Pre-index addressingLDR R0, [R1, #4] @ R0=mem[R1+4]@ R1 nchanged@ R1 unchanged LDR R0,[R1, ]LDR R0,[R1, ]R1+R0 Auto-indexing addressingLDR R0, [R1, #4]! @ R0=mem[R1+4]@R1R1+4@ R1=R1+4No extra time; Fast; LDR R0,[R1, ]!;;LDR R0,[R1, ]!R1+R0 Post-index addressingLDR R0, R1, #4@ R0=mem[R1]@R1R1+4@ R1=R1+4 LDR R0,[R1],LDR R0,[R1],R0R1+Comparisons Pre-indexed addressingLDR R0[R1 R2]@ R0=mem[R1+R2]LDR R0, [R1, R2] @ R0=mem[R1+R2]@ R1 unchangedAutoindexing addressing Auto-indexing addressingLDR R0, [R1, R2]! @ R0=mem[R1+R2]@ R1 R1+R2@ R1=R1+R2 Post-indexed addressingLDR R0, [R1], R2@ R0=mem[R1]@ R1=R1+R2 ExampleExampleExampleSummary of addressing modesSummary of addressing modesSummary of addressing modesSummary of addressing modesLoad an address into a register Note that all addressing modes are register-offseted Can we issue LDR R0 Table?