ARMv8 A64 Quick Reference Conditional Instructions

1 ARM64 version 2 page 1 ARMv8 A64 Quick ReferenceArithmetic InstructionsADC{S}rd, rn, rmrd = rn + rm + CADD{S}rd, rn, op2rd = rn + op2 SADRXd, rel21Xd = PC + rel ADRPXd, rel33Xd = PC63:12:012+ rel 33:12:012 CMNrd, op2rd + op2 SCMPrd, op2rd op2 SMADDrd, rn, rm, rard = ra + rn rmMNEGrd, rn, rmrd = rn rmMSUBrd, rn, rm, rard = ra rn rmMULrd, rn, rmrd = rn rmNEG{S}rd, op2rd = op2 NGC{S}rd, rmrd = rm CSBC{S}rd, rn, rmrd = rn rm CSDIVrd, rn, rmrd = rn rmSMADDLXd, Wn, Wm, XaXd = Xa + Wn WmSMNEGLXd, Wn, WmXd = Wn WmSMSUBLXd, Wn, Wm, XaXd = Xa Wn WmSMULHXd, Xn, XmXd = (Xn Xm)127:64 SMULLXd, Wn, WmXd = Wn WmSUB{S}rd, rn, op2rd = rn - op2 SUDIVrd, rn, rmrd = rn rmUMADDLXd, Wn, Wm, XaXd = Xa + Wn WmUMNEGLXd, Wn, WmXd = Wn WmUMSUBLXd, Wn, Wm, XaXd = Xa Wn WmUMULHXd, Xn, XmXd = (Xn Xm)127:64 UMULLXd, Wn, WmXd = Wn WmBit Manipulation InstructionsBFIrd, rn, #p, #nrdp+n 1:p= rnn 1:0 BFXILrd, rn, #p, #nrdn 1:0= rnp+n 1:pCLSrd, rnrd = CountLeadingOnes(rn)CLZrd, rnrd = CountLeadingZeros(rn)EXTRrd, rn, rm, #prd = rnp 1:0:rmN0 RBITrd, rnrd = ReverseBits(rn)REVrd, rnrd = BSwap(rn)REV16rd, rnfor(n= |3) rdHn=BSwap(rnHn)REV32Xd, XnXd=BSwap(Xn63:32):BSwap(Xn31:0){S,U}BF IZrd, rn, #p, #nrd = rn?

2 N 1:0 p{S,U}BFXrd, rn, #p, #nrd = rn?p+n 1:p{S,U}XT{B,H}rd, Wnrd = Wn?N0 SXTWXd, WnXd = Wn Logical and Move InstructionsAND{S}rd, rn, op2rd = rn & op2 ASRrd, rn, rmrd = rn rmASRrd, rn, #i6rd = rn iBIC{S}rd, rn, op2rd = rn & op2 EONrd, rn, op2rd = rn op2 EORrd, rn, op2rd = rn op2 LSLrd, rn, rmrd = rn rmLSLrd, rn, #i6rd = rn iLSRrd, rn, rmrd = rn rmLSRrd, rn, #i6rd = rn iMOVrd, rnrd = rnSMOVrd, #ird = iMOVKrd,#i16{, sh}rdsh+15:sh= iMOVNrd,#i16{, sh}rd = (i sh)MOVZrd,#i16{, sh}rd = i shMVNrd, op2rd = op2 ORNrd, rn, op2rd = rn| op2 ORRrd, rn, op2rd = rn|op2 RORrd, rn, #i6rd = rn iRORrd, rn, rmrd = rn rmTSTrn, op2rn & op2 Branch InstructionsBrel28PC = PC + rel 27:2:02 Bccrel21if(cc) PC = PC + rel 20:2:02 BLrel28X30 = PC + 4; PC += rel 27:2:02 BLRXnX30 = PC + 4; PC = XnBRXnPC = XnCBNZrn, rel21if(rn6= 0) PC += rel 21:2:02 CBZrn, rel21if(rn = 0) PC += rel 21:2:02 RET{Xn}PC = XnTBNZrn, #i, rel16if(rni6= 0) PC += rel 15:2:02 TBZrn, #i, rel16if(rni= 0) PC += rel 15:2:02 Atomic InstructionsCAS{A}{L}rs, rt, [Xn]if (rs = [Xn]N) [Xn]N= rt1 CAS{A}{L}{B,H}Ws, Wt, [Xn]if (WsN0= [Xn]N) [Xn]N= WtN01 CAS{A}{L}Prs,rs2,rt,rt2,[Xn]if (rs2:rs = [Xn]2N) [Xn]2N= rt2:rt1 LDao{A}{L}{B,H}Ws, Wt, [Xn]Wt=[Xn] N; [Xn]N=ao([Xn]N,WsN0)1 LDao{A}{L}rs, rt, [Xn]rt = [Xn]N; [Xn]N= ao([Xn]N, rs)1 STao{A}{L}{B,H}Ws, [Xn][Xn]N= ao([Xn]N, WsN0)1 STao{A}{L}rs, [Xn][Xn]N= ao([Xn]N, rs)1 SWP{A}{L}{B,H}Ws, Wt, [Xn]Wt = [Xn] N; [Xn]N= WsN01 SWP{A}{L}rs, rt, [Xn]rt = [Xn]N; [Xn]N= rs1 Conditional InstructionsCCMNrn, #i5, #f4, ccif(cc) rn + i.

3 Else N:Z:C:V = fCCMNrn, rm, #f4, ccif(cc) rn + rm; else N:Z:C:V = fCCMPrn, #i5, #f4, ccif(cc) rn i; else N:Z:C:V = fCCMPrn, rm, #f4, ccif(cc) rn rm; else N:Z:C:V = fCINCrd, rn, ccif(cc) rd = rn + 1; else rd = rnCINVrd, rn, ccif(cc) rd = rn; else rd = rnCNEGrd, rn, ccif(cc) rd = rn; else rd = rnCSELrd, rn, rm, ccif(cc) rd = rn; else rd = rmCSETrd, ccif(cc) rd = 1; else rd = 0 CSETMrd, ccif(cc) rd = 0; else rd = 0 CSINCrd, rn, rm, ccif(cc) rd = rn; else rd = rm + 1 CSINVrd, rn, rm, ccif(cc) rd = rn; else rd = rmCSNEGrd, rn, rm, ccif(cc) rd = rn; else rd = rmLoad and Store InstructionsLDPrt, rt2, [addr]rt2:rt = [addr]2 NLDPSWXt, Xt2, [addr]Xt = [addr] 32; Xt2 = [addr+4] 32LD{U}Rrt, [addr]rt = [addr]NLD{U}R{B,H}Wt, [addr]Wt = [addr] NLD{U}RS{B,H}rt, [addr]rt = [addr] NLD{U}RSWXt, [addr]Xt = [addr] 32 PRFM prfop, addrPrefetch(addr, prfop)STPrt, rt2, [addr][addr]2N= rt2:rtST{U}Rrt, [addr][addr]N= rtST{U}R{B,H}Wt, [addr][addr]N= WtN0 Addressing Modes (addr)xxP,LDPSW[Xn{, #i7+s}]addr = Xn + i 6+s:s:0sxxP,LDPSW[Xn], #i7+saddr=Xn; Xn+=i 6+s:s:0sxxP,LDPSW[Xn, #i7+s]!

4 Xn+=i 6+s:s:0s; addr=XnxxR*,PRFM[Xn{, #i12+s}]addr = Xn + i 11+s:s:0sxxR*[Xn], #i9addr = Xn; Xn += i xxR*[Xn, #i9]!Xn += i ; addr = XnxxR*,PRFM[Xn,Xm{, LSL #0|s}]addr = Xn + Xm sxxR*,PRFM[Xn,Wm,{S,U}XTW{#0|s}]addr = Xn + Wm? sxxR*,PRFM[Xn,Xm,SXTX{#0|s}]addr = Xn + Xm sxxUR*,PRFM[Xn{, #i9}]addr = Xn += i LDR{SW},PRFM rel21addr = PC + rel 20:2:02 Atomic Operations (ao)ADD[Xn] + rsSMAX[Xn] >rs ? [Xn] : rsCLR[Xn] & rsSMIN[Xn] <rs ? [Xn] : rsEOR[Xn] rsUMAX[Xn]>rs ? [Xn] : rsSET[Xn]|rsUMIN[Xn]<rs ? [Xn] : rs1 ARM64 version 2 page 2 Operand 2 (op2)allrmrmallrm, LSL #i6rm iallrm, LSR #i6rm iallrm, ASR #i6rm ilogicalrm, ROR #i6rm iarithmeticWm,{S,U}XTB{#i3}Wm?B0 iarithmeticWm,{S,U}XTH{#i3}Wm?H0 iarithmeticWm,{S,U}XTW{#i3}Wm? iarithmeticXm,{S,U}XTX{#i3}Xm? iarithmetic#i12i arithmetic#i24i 23:12:012 AND,EOR,ORR,TST#maskmaskRegistersX0-X7 Arguments and return valuesX8 Indirect resultX9-X15 TemporaryX16-X17 Intra-procedure-call temporaryX18 Platform defined useX19-X28 Temporary (must be preserved)X29 Frame pointer (must be preserved)X30 Return addressSPStack pointerXZRZeroPCProgram counterSpecial Purpose RegistersSPSREL{ }Process state on exception entry to EL{ }64 ELREL{ }Exception return address from EL{ }SPEL{ }Stack pointer for EL{ }64 SPSelSP selection (0: SP=SPEL0, 1.)

5 SP=SPELn)CurrentELCurrent Exception level (at bits )RODAIFC urrent interrupt mask bits (at bits )NZCVC ondition flags (at bits )FPCRF loating-point operation controlFPSRF loating-point statusKeysNOperand bit size (8, 16, 32 or 64)sOperand log byte size (0=byte,1=hword,2=word,3=dword)rd, rn, rm, rtGeneral register of either size (Wn or Xn)prfopP{LD,LI,ST}L{ }{KEEP,STRM}{,sh}Optional halfword left shift (LSL #{16,32,48})val , val , val?Value is sign/zero extended (? depends on instruction) > <Operation is signedChecksum InstructionsCRC32{B,H}Wd, Wn, WmWd=CRC32(Wn,0x04c11db7,WmN0)CRC32 WWd, Wn, WmWd = CRC32(Wn,0x04c11db7,Wm)CRC32 XWd, Wn, XmWd = CRC32(Wn,0x04c11db7,Xm)CRC32C{B,H}Wd, Wn, WmWd=CRC32(Wn,0x1edc6f41,WmN0)CRC32 CWWd, Wn, WmWd = CRC32(Wn,0x1edc6f41,Wm)CRC32 CXWd, Wn, XmWd = CRC32(Wn,0x1edc6f41,Xm)Load and Store Instructions with AttributeLD{A}XPrt, rt2, [Xn]rt:rt2 = [Xn,<SetExclMonitor>]2 NLD{A}{X}Rrt, [Xn]rt = [Xn,<SetExclMonitor>]NLD{A}{X}R{B,H}Wt, [Xn]Wt = [Xn,<SetExclMonitor>] NLDNPrt,rt2,[Xn{,#i7+s}]rt2:rt = [Xn + i 6+s:s.]

6 0s,<Temp>]2 NLDTRrt, [Xn{, #i9}]rt = [Xn += i ,<Unpriv>]NLDTR{B,H}Wt, [Xn{, #i9}]Wt = [Xn += i ,<Unpriv>] NLDTRS{B,H}rt, [Xn{, #i9}]rt = [Xn += i ,<Unpriv>] NLDTRSWXt, [Xn{, #i9}]Xt = [Xn += i ,<Unpriv>] 32 STLRrt, [Xn][Xn,<Release>]N= rtSTLR{B,H}Wt, [Xn][Xn,<Release>]N= WtN0ST{L}XPWd, rt, rt2, [Xn][Xn,<Excl>]2N=rt:rt2; Wd=fail?1:0ST{L}XRWd, rt, [Xn][Xn,<Excl>]N=rt; Wd=fail?1:0ST{L}XR{B,H}Wd, Wt, [Xn][Xn,<Excl>]N=WtN0; Wd=fail?1:0 STNPrt,rt2,[Xn{,#i7+s}][Xn + i 6+s:s:0s,<Temp>]2N= rt2:rtSTTRrt, [Xn{, #i9}][Xn += i ,<Unpriv>]N= rtSTTR{B,H}Wt, [Xn{, #i9}][Xn += i ,<Unpriv>]N= WtN0 Condition Codes (cc)EQEqualZNENot equal!ZCS/HSCarry set, Unsigned higher or sameCCC/LOCarry clear, Unsigned lower!CMIM inus, NegativeNPLPlus, Positive or zero!NVSO verflowVVCNo overflow!VHIU nsigned higherC & !ZLSU nsigned lower or same!

7 C|ZGES igned greater than or equalN = VLTS igned less thanN6= VGTS igned greater than!Z & N = VLES igned less than or equalZ|N6= VALA lways (default)1 Notes for Instruction SetSSP/WSP may be used as operand(s) instead of XZR/WZR1 Introduced in InstructionsATS1{2}E{ }{R,W}, XnPAREL1 = AddrTrans(Xn)BRK#i16 SoftwareBreakpoint(i)CLREX{#i4}ClearExcl usiveLocal()DMBbarrieropDataMemoryBarrie r(barrierop)DSBbarrieropDataSyncBarrier( barrierop)ERETPC=ELRELn;PSTATE=SPSRELnHV C#16 CallHypervisor(i)ISB{SY}InstructionSyncB arrier(SY)MRSXd, sysregXd = sysregMSRsysreg, Xnsysreg = XnMSRSPSel, # = iMSRDAIFSet, # |= iMSRDAIFClr, # &= iNOPSEVSendEvent()SEVLE ventRegisterSet()SMC#i16 CallSecureMonitor(i)SVC#i16 CallSupervisor(i)WFEWaitForEvent()WFIWai tForInterrupt()YIELDC ache and TLB Maintenance InstructionsDC{C,CI,I}SW, XxDC clean and/or inv by Set/WayDC{C,CI,I}VAC, XxDC clean and/or inv by VA to PoCDCCVAU, XxDC clean by VA to PoUDCZVA, XxDC zero by VA (len in DCZIDEL0)

8 ICIALLU{IS}IC inv all to PoUICIVAU, XxIC inv VA to PoUTLBIALLE{ }{IS}TLB inv allTLBIASIDE1{IS}, XxTLB inv by ASIDTLBIIPAS2{L}E1{IS}, XxTLB inv by IPA{last level}TLBIVAA{L}E1{IS}, XxTLB inv by VA, all ASID{last level}TLBIVA{L}E{ }{IS}, XxTLB inv by VA{last level}TLBIVMALL{S12}E1{IS}TLB inv by VMID, all, at stage 1{&2}DMB and DSB OptionsOSH{,LD,ST}Outer shareable,{all,load,store}NSH{,LD,ST}Non -shareable,{all,load,store}ISH{,LD,ST}In ner shareable,{all,load,store}LDFull system, loadSTFull system, storeSYFull system, all2 ARM64 version 2 page 3 ARMv8 -A SystemControl and Translation RegistersSCTLREL{ }System ControlACTLREL{ }Auxiliary Control64 CPACREL1 Architectural Feature Access ControlHCREL2 Hypervisor Configuration64 CPTREL{2,3}Architectural Feature TrapHSTREL2 Hypervisor System TrapHACREL2 Hypervisor Auxiliary ControlSCREL3 Secure ConfigurationTTBR0EL{ }Translation Table Base 0 (4/16/64kb aligned)64 TTBR1EL1 Translation Table Base 1 (4/16/64kb aligned)64 TCREL{ }Translation Control64 VTTBREL2 Virt Translation Table Base (4/16/64kb aligned)64 VTCREL2 Virt Translation Control{A}MAIREL{ }{Auxiliary}Memory Attribute Indirection64 LOR{S,E}AEL1 LORegion{Start,End}Address64,1 LOR{C,N,ID}EL1 LORegion{Control,Number,ID}64,1 Exception RegistersAFSR{0,1}EL{ }Auxiliary Fault Status{0,1}ESREL{ }Exception SyndromeFAREL{ }Fault Address64 HPFAREL2 Hypervisor IPA Fault Address64 PAREL1 Physical Address64 VBAREL{ }Vector Base Address (2kb aligned)

9 64 RVBAREL{ }Reset Vector Base AddressRO,64 RMREL{ }Reset ManagementISREL1 Interrupt StatusROPerformance Monitors RegistersPMCREL0PM ControlPMCNTEN{SET,CLR}EL0PM Count Enable{Set,Clear}PMOVSCLREL0PM Overflow Flag Status ClearPMSWINCEL0PM Software IncrementWOPMSELREL0PM Event Counter SelectionPMCEID{0,1}EL0PM Common Event ID{0,1}ROPMCCNTREL0PM Cycle Count Register64 PMXEVTYPEREL0PM Selected Event TypePMXEVCNTREL0PM Selected Event CountPMUSERENREL0PM User EnablePMOVSSETEL0PM Overflow Flag Status SetPMINTEN{SET,CLR}EL1PM Interrupt Enable{Set,Clear}PMEVCNTR{ }EL0PM Event Count{ }PMEVTYPER{ }EL0PM Event Type{ }PMCCFILTREL0PM Cycle Count FilterID RegistersMIDREL1 Main IDROMPIDREL1 Multiprocessor AffinityRO,64 REVIDREL1 Revision IDROCCSIDREL1 Current Cache Size IDROCLIDREL1 Cache Level IDROAIDREL1 Auxiliary IDROCSSELREL1 Cache Size SelectionCTREL0 Cache TypeRODCZIDEL0 Data Cache Zero IDROVPIDREL2 Virtualization Processor IDVMPIDREL2 Virtualization Multiprocessor ID64 IDAA64 PFR{0,1}EL1 AArch64 Processor Feature{0,1}RO,64 IDAA64 DFR{0,1}EL1 AArch64 Debug Feature{0,1}RO,64 IDAA64 AFR{0,1}EL1 AArch64 Auxiliary Feature{0,1}RO,64 IDAA64 ISAR{0,1}EL1 AArch64 Instruction Set Attribute{0,1}RO,64 IDAA64 MMFR{0,1}EL1 AArch64 Memory Model Feature{0,1}RO,64 CONTEXTIDREL1 Context IDTPIDREL{ }Software Thread ID64 TPIDRROEL0EL0 Read-only Software Thread ID64 Exception Vectors0x000,0x080,0x100,0x180{Sync,IRQ, FIQ,SError}from cur lvl with SPEL00x200,0x280,0x300,0x380{Sync,IRQ,FI Q.}

10 SError}from cur lvl with SPELn0x400,0x480,0x500,0x580{Sync,IRQ,FI Q,SError}from lower lvl using A640x600,0x680,0x700,0x780{Sync,IRQ,FIQ, SError}from lower lvl using A32 System Control Register (SCTLR)M0x00000001 MMU enabledA0x00000002 Alignment check enabledC0x00000004 Data and unified caches enabledSA0x00000008 Enable SP alignment checkSA00x00000010 Enable SP alignment check for EL0E1 UMA0x00000200 Trap EL0 access of DAIF to EL1E1I0x00001000 Instruction cache enabledDZE0x00004000 Trap EL0 DC instruction to EL1E1 UCT0x00008000 Trap EL0 access of CTREL0 to EL1E1nTWI0x00010000 Trap EL0 WFI instruction to EL1E1nTWE0x00040000 Trap EL0 WFE instruction to EL1E1 WXN0x00080000 Write permission implies XNSPAN0x00800000 Set privileged access neverE1,1E0E0x01000000 Data at EL0 is big-endianE1EE0x02000000 Data at EL1 is big-endianUCI0x04000000 Trap EL0 cache Instructions to EL1E1 Generic Timer RegistersCNTFRQEL0Ct Frequency (in Hz)