AXI GPIO v2 - Xilinx

1 AXI GPIO LogiCORE IP Product Guide Vivado Design Suite PG144 October 5, 2016. Table of Contents IP Facts Chapter 1: Overview Functional Description.. 5. Applications .. 6. Licensing and Ordering Information .. 6. Chapter 2: Product Specification Port Descriptions .. 9. Register Space .. 10. Interrupts .. 12. Chapter 3: Designing with the Core Operation .. 15. Programming Sequence.. 16. Clocking.. 16. Resets .. 16. Chapter 4: Design Flow Steps Customizing and Generating the Core .. 17. Constraining the Core .. 21. Simulation .. 22. Synthesis and Implementation .. 22. Chapter 5: Example Design Overview .. 23. Implementing the Example Design .. 25. Example Design Files .. 25. Test Bench .. 26. Simulating the Example Design.. 27. Appendix A: Migrating and Upgrading Migrating to the Vivado Design Suite.. 28. Upgrading in the Vivado Design Suite .. 28. AXI GPIO Send Feedback 2. PG144 October 5, 2016 Appendix B: Debugging Finding Help on.

2 29. Vivado Design Suite Debug Feature .. 30. Hardware Debug .. 31. AXI4-Lite Interface Debug .. 31. Appendix C: Additional Resources and Legal Notices Xilinx Resources .. 32. References .. 32. Revision History .. 33. Please Read: Important Legal Notices .. 34. AXI GPIO Send Feedback 3. PG144 October 5, 2016 IP Facts Introduction LogiCORE IP Facts Table Core Specifics The Xilinx LogiCORE IP AXI General Purpose UltraScale+ . Input/Output (GPIO) core provides a general Supported UltraScale . purpose input/output interface to the AXI Device Family(1) Zynq -7000 All Programmable SoC, interface. This 32-bit soft Intellectual Property 7 Series FPGAs (IP) core is designed to interface with the Supported User AXI4-Lite Interfaces AXI4-Lite interface. Resources See Table 2-2. Provided with Core Features Design Files VHDL. Example Design VHDL. Supports the AXI4-Lite interface Test Bench VHDL. specification Constraints File Xilinx Design Constraints (XDC).

3 Supports configurable single or dual GPIO Simulation Not Provided channel (s) Model Supported Supports configurable channel width for Standalone and Linux S/W Driver (2). GPIO pins from 1 to 32 bits Tested Design Flows(3). Supports dynamic programming of each Design Entry Vivado Design Suite GPIO bit as input or output For a list of supported simulators, see the Simulation Xilinx Design Tools: Release Notes Guide Supports individual configuration of each Synthesis Vivado Synthesis channel Support Supports independent reset values for each Provided by Xilinx at the Xilinx Support web page bit of all registers Notes: Supports optional interrupt request 1. For a complete list of supported devices, see the Vivado IP. generation catalog. 2. Standalone driver details can be found in the software development kit (SDK) directory <install_directory>/SDK/<release>/data/embeddedsw/doc/x ). Linux OS and driver support information is available from the Linux GPIO Driver page.

4 3. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide. AXI GPIO Send Feedback 4. PG144 October 5, 2016 Product Specification Chapter 1. Overview Functional Description The AXI GPIO design provides a general purpose input/output interface to an AXI4-Lite interface. The AXI GPIO can be configured as either a single or a dual- channel device. The width of each channel is independently configurable. The ports are configured dynamically for input or output by enabling or disabling the 3-state buffer. The channels can be configured to generate an interrupt when a transition on any of their inputs occurs. The top-level block diagram of AXI GPIO core is shown in Figure 1-1. X-Ref Target - Figure 1-1. AXI GPIO. GPIO CORE. GPIO_TRI. D Q GPIO_WIDTH. GPIO_T. GPIO_DAT. A. D Q GPIO_WIDTH GPIO_O. AXI4 Lite Interface GPIO_DATA_IN. D Q GPIO_I. MUX. GPIO_WIDTH. S_AXI. READ_REG.

5 GPIO_TRI. D Q GPIO2_WIDTH. GPIO2_T. GPIO_DATA. Interrupt D Q GPIO2_WIDTH GPIO2_O. Registers ip2intc_irpt GPIO_DATA_IN. Interrupt D Q GPIO2_WIDTH GPIO2_I. Detection X13238. Figure 1-1: AXI GPIO Block Diagram AXI GPIO Send Feedback 5. PG144 October 5, 2016 Chapter 1: Overview AXI4-Lite Interface The AXI4-Lite Interface module implements a 32-bit AXI4-Lite slave interface for accessing GPIO channel registers. For additional details about the AXI4-Lite slave interface, see the specification usage section of the AXI4-Lite IPIF LogiCORE IP Product Guide (PG155) [Ref 1]. Interrupt Control Interrupt control gets the interrupt status from GPIO channels and generates an interrupt to host. It is enabled when the Enable Interrupt option is set in the Vivado Integrated Design Environment (IDE). GPIO Core The GPIO core consists of registers and multiplexers for reading and writing the AXI GPIO. channel registers.

6 It also includes the necessary logic to identify an interrupt event when the channel input changes. The 3-state buffers in the figure are not actually part of the core. The 3-state buffers are automatically added in top level design wrapper file, when you generate the output product in the Vivado Design Suite. Applications The General Purpose Input/output (GPIO) core is an interface that provides an ease of access to the internal properties of the device. Similarly this core can be used to control the behavior of external devices. Licensing and Ordering Information This Xilinx LogiCORE IP module is provided at no additional cost with the Xilinx Vivado Design Suite under the terms of the Xilinx End User License. Information about this and other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual Property page. For information on pricing and availability of other Xilinx LogiCORE IP modules and tools, contact your local Xilinx sales representative.

7 AXI GPIO Send Feedback 6. PG144 October 5, 2016 Chapter 2. Product Specification Performance characterization of the AXI GPIO core has been done using the margin system methodology. The details of the margin system characterization are described in the Vivado IP Optimization (Fmax Characterization) appendix in the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 2] . The summary of performance F MAX is shown in Table 2-1. Note: Performance numbers for Zynq -7000 and UltraScale devices are expected to be similar to 7 series device numbers. Table 2-1: 7 Series Performance Characterizations Family Speed Grade Fmax (MHz). AXI4-Lite Virtex -7 180. Kintex -7 -1 180. Artix -7 120. Virtex-7 200. Kintex-7 -2 200. Artix-7 140. Virtex-7 220. Kintex-7 -3 220. Artix-7 160. AXI GPIO Send Feedback 7. PG144 October 5, 2016 Chapter 2: Product Specification Table 2-2 shows the resource utilization for AXI GPIO for 7 series FPGAs.

8 These values were generated using the Vivado Design Suite. Note: Resource utilization numbers for Zynq-7000 devices and UltraScale architecture are expected to be similar to 7 series FPGAs. Table 2-2: Resource Utilization for 7 Series FPGAs Parameter Values (Other Parameters at Default Value) Device Resources Enable Dual Enable Interrupt GPIO Width GPIO2 GPIO Slices Flip-Flops LUTs channel Width 0 0 32 32 34 174 124. 0 0 16 32 21 94 72. 0 1 32 16 40 179 135. 0 1 32 32 36 179 135. 0 1 1 1 9 24 28. 1 0 32 32 66 302 230. 1 0 1 1 8 23 25. 1 0 5 28 40 174 134. 1 0 28 5 41 174 131. 1 1 32 32 65 307 249. 1 1 15 28 52 219 171. 1 1 1 1 12 28 33. AXI GPIO Send Feedback 8. PG144 October 5, 2016 Chapter 2: Product Specification Port Descriptions The AXI GPIO I/O signals are listed and described in Table 2-3. Table 2-3: AXI GPIO Signal Description Initial Signal Name Interface I/O Description State s_axi_aclk Clock I AXI Clock.

9 S_axi_aresetn Reset I AXI Reset, active-Low. AXI4-Lite Slave Interface signals. s_axi_* S_AXI NA - See Appendix A of the Vivado AXI Reference Guide (UG1037). [Ref 3] for AXI4, AXI4-Lite and AXI Stream Signals ip2intc_irpt System O 0 AXI GPIO Interrupt. active-High, level sensitive signal. channel 1 general purpose input pins. gpio_io_i (1)(3) GPIO I. Width of this port is configurable based on GPIO Width. channel 1 general purpose output pins. gpio_io_o (2)(3)(4) GPIO O 0. Width of this port is configurable based on GPIO Width. channel 1 general purpose 3-state pins. gpio_io_t (4) GPIO O 1. Width of this port is configurable based on GPIO Width. channel 2 general purpose input pins. gpio2_io_i (1)(3) GPIO I. Width of this port is configurable based on GPIO2 Width. channel 2 general purpose output pins. gpio2_io_o (2)(3)(4) GPIO O 0. Width of this port is configurable based on GPIO2 Width. channel 2 general purpose 3-state pins gpio2_io_t (4) GPIO O 1.

10 Width of this port is configurable based on GPIO2 Width. Notes: 1. If only input ports are needed, you can edit the ports in the block diagram, and declare at port interface level. 2. If only output ports are needed, you can get these ports to port interface. 3. By default, the Vivado Design Suite (IP integrator) auto inserts a 3-state buffer which is available in the top of the HDL file after you generate the wrapper file. 4. You can choose the default value of the general purpose outputs (*io_o, *io_t) while customizing the core. AXI GPIO Send Feedback 9. PG144 October 5, 2016 Chapter 2: Product Specification Register Space Note: The AXI4-Lite write access register is updated by the 32-bit AXI Write Data (*_wdata) signal, and is not impacted by the AXI Write Data Strobe (*_wstrb) signal. For a Write, both the AXI Write Address Valid (*_awvalid) and AXI Write Data Valid (*_wvalid) signals should be asserted together.