AXI GPIO v2 - Xilinx - All Programmable

1 AXI gpio IP product GuideVivado Design SuitePG144 October 5, 2016 AXI gpio October 5, of ContentsIP FactsChapter 1: OverviewFunctional Description.. 5 Applications .. 6 Licensing and Ordering Information .. 6 Chapter 2: product SpecificationPort Descriptions .. 9 Register Space .. 10 Interrupts .. 12 Chapter 3: Designing with the CoreOperation .. 15 Programming Sequence.. 16 Clocking.. 16 Resets .. 16 Chapter 4: Design Flow StepsCustomizing and Generating the Core .. 17 Constraining the Core .. 21 Simulation .. 22 Synthesis and Implementation .. 22 Chapter 5: Example DesignOverview .. 23 Implementing the Example Design .. 25 Example Design Files .. 25 Test Bench .. 26 Simulating the Example Design.. 27 Appendix A: Migrating and UpgradingMigrating to the vivado Design Suite .. 28 Upgrading in the vivado Design Suite .. 28 Send FeedbackAXI gpio October 5, B: DebuggingFinding Help on .. 29 vivado Design Suite Debug Feature.

2 30 Hardware Debug .. 31 AXI4-Lite Interface Debug .. 31 Appendix C: Additional Resources and Legal NoticesXilinx Resources .. 32 References .. 32 Revision History .. 33 Please Read: Important Legal Notices .. 34 Send FeedbackAXI gpio October 5, SpecificationIntroductionThe Xilinx logicore IP AXI General Purpose Input/Output ( gpio ) core provides a general purpose input/output interface to the AXI interface. This 32-bit soft Intellectual Property (IP) core is designed to interface with the AXI4-Lite Supports the AXI4-Lite interface specification Supports configurable single or dual gpio channel(s) Supports configurable channel width for gpio pins from 1 to 32 bits Supports dynamic programming of each gpio bit as input or output Supports individual configuration of each channel Supports independent reset values for each bit of all registers Supports optional interrupt request generationIP FactsLogiCORE IP Facts TableCore SpecificsSupported Device Family(1)UltraScale+ UltraScale Zynq -7000 All Programmable SoC,7 Series FPGAsSupported User InterfacesAXI4-LiteResourcesSee Table 2-2 Provided with CoreDesign FilesVHDLE xample DesignVHDLTest BenchVHDLC onstraints FileXilinx Design Constraints (XDC)Simulation ModelNot ProvidedSupported S/W Driver(2)Standalone and LinuxTested Design Flows(3)

3 Design EntryVivado Design SuiteSimulationFor a list of supported simulators, see theXilinx Design Tools: Release Notes GuideSynthesisVivado SynthesisSupportProvided by Xilinx at the Xilinx Support web pageNotes: 1. For a complete list of supported devices, see the vivado IP Standalone driver details can be found in the software development kit (SDK) directory<install_directory>/SDK/<release>/data/embeddedsw/ ) Linux OS and driver support information is available from the Linux gpio Driver For the supported versions of the tools, see theXilinx Design Tools: Release Notes FeedbackAXI gpio October 5, 1 OverviewFunctional DescriptionThe AXI gpio design provides a general purpose input/output interface to an AXI4-Lite interface. The AXI gpio can be configured as either a single or a dual-channel device. The width of each channel is independently ports are configured dynamically for input or output by enabling or disabling the 3-state buffer. The channels can be configured to generate an interrupt when a transition on any of their inputs top-level block diagram of AXI gpio core is shown in Figure 1-1.

4 X-Ref Target - Figure 1-1 Figure 1-1:AXI gpio Block DiagramAXI GPIOGPIO COREGPIO_WIDTHGPIO_WIDTHGPIO_DATAGPIO_WI DTHGPIO2_WIDTHGPIO2_WIDTHGPIO2_WIDTHGPIO _TGPIO_OGPIO_IGPIO2_TGPIO2_OGPIO2_IREAD_ REGAXI4 Lite InterfaceInterrupt DetectionInterrupt RegistersMUXS_AXIip2intc_irptDQGPIO_TRID QGPIO_DATA_INDQDQGPIO_DATADQGPIO_TRIDQGP IO_DATA_INX13238 Send FeedbackAXI gpio October 5, 1:OverviewAXI4-Lite InterfaceThe AXI4-Lite Interface module implements a 32-bit AXI4-Lite slave interface for accessing gpio channel registers. For additional details about the AXI4-Lite slave interface, see the specification usage section of the AXI4-Lite IPIF logicore IP product guide (PG155) [Ref 1].Interrupt ControlInterrupt control gets the interrupt status from gpio channels and generates an interrupt to host. It is enabled when the Enable Interrupt option is set in the vivado Integrated Design Environment (IDE). gpio CoreThe gpio core consists of registers and multiplexers for reading and writing the AXI gpio channel registers.

5 It also includes the necessary logic to identify an interrupt event when the channel input 3-state buffers in the figure are not actually part of the core. The 3-state buffers are automatically added in top level design wrapper file, when you generate the output product in the vivado Design The General Purpose Input/output ( gpio ) core is an interface that provides an ease of access to the internal properties of the device. Similarly this core can be used to control the behavior of external and Ordering InformationThis Xilinx logicore IP module is provided at no additional cost with the Xilinx vivado Design Suite under the terms of the Xilinx End User License. Information about this and other Xilinx logicore IP modules is available at the Xilinx Intellectual Property page. For information on pricing and availability of other Xilinx logicore IP modules and tools, contact your local Xilinx sales FeedbackAXI gpio October 5, 2 product SpecificationPerformance characterization of the AXI gpio core has been done using the margin system methodology.

6 The details of the margin system characterization are described in the vivado IP Optimization (Fmax Characterization) appendix in the vivado Design Suite User guide : Designing with IP (UG896) [Ref 2].The summary of performance FMAX is shown in Table :Performance numbers for Zynq -7000 and UltraScale devices are expected to be similar to 7 series device 2-1:7 Series Performance CharacterizationsFamilySpeed GradeFmax (MHz)AXI4-LiteVirtex -7-1180 Kintex -7180 Artix -7120 Virtex-7-2200 Kintex-7200 Artix-7140 Virtex-7-3220 Kintex-7220 Artix-7160 Send FeedbackAXI gpio October 5, 2: product SpecificationTable 2-2 shows the resource utilization for AXI gpio for 7 series FPGAs. These values were generated using the vivado Design Suite. Note:Resource utilization numbers for Zynq-7000 devices and UltraScale architecture are expected to be similar to 7 series 2-2:Resource Utilization for 7 Series FPGAsParameter Values (Other Parameters at Default Value)Device ResourcesEnable Dual ChannelEnable InterruptGPIO WidthGPIO2 gpio WidthSlicesFlip-FlopsLUTs00323234 174 124 00163221 94 72 01321640 179 135 01323236 179 135 01119 24 28 10323266 302 230 10118 23 25 1052840 174 134 1028541 174 131 11323265 307 249 11152852 219 171 111112 28 33 Send FeedbackAXI gpio October 5, 2.

7 product SpecificationPort DescriptionsThe AXI gpio I/O signals are listed and described in Table 2-3:AXI gpio Signal Description Signal NameInterfaceI/OInitial StateDescriptions_axi_aclkClockI AXI AXI Reset, *S_AXINA- AXI4-Lite Slave Interface Appendix A of the vivado AXI Reference guide (UG1037) [Ref 3] for AXI4, AXI4-Lite and AXI Stream Signalsip2intc_irptSystemO0 AXI gpio Interrupt. active-High, level sensitive (1)(3)GPIOI Channel 1 general purpose input pins. Width of this port is configurable based on gpio (2)(3)(4)GPIOO0 Channel 1 general purpose output of this port is configurable based on gpio (4)GPIOO1 Channel 1 general purpose 3-state of this port is configurable based on gpio (1)(3)GPIOI Channel 2 general purpose input of this port is configurable based on GPIO2 (2)(3)(4)GPIOO0 Channel 2 general purpose output of this port is configurable based on GPIO2 (4)GPIOO1 Channel 2 general purpose 3-state pinsWidth of this port is configurable based on GPIO2 : 1.

8 If only input ports are needed, you can edit the ports in the block diagram, and declare at port interface If only output ports are needed, you can get these ports to port By default, the vivado Design Suite (IP integrator) auto inserts a 3-state buffer which is available in the top of the HDL file after you generate the wrapper You can choose the default value of the general purpose outputs (*io_o, *io_t) while customizing the FeedbackAXI gpio October 5, 2: product SpecificationRegister SpaceNote:The AXI4-Lite write access register is updated by the 32-bit AXI Write Data (*_wdata) signal, and is not impacted by the AXI Write Data Strobe (*_wstrb) signal. For a Write, both the AXI Write Address Valid (*_awvalid) and AXI Write Data Valid (*_wvalid) signals should be asserted together. Also see Answer Record 2-4 shows the AXI gpio registers and their on the value of certain configuration parameters, some of these registers are removed. A write to an unimplemented register has no effect.

9 An attempt to read the unimplemented register returns an all zero value. The register dependencies of these parameters are described in Table 2-5. Table 2-4:RegistersAddress Space Offset(3) Register NameAccess TypeDefault Value Description0x0000 GPIO_DATAR/W0x0 Channel 1 AXI gpio Data 1 AXI gpio 3-state Control 2 AXI gpio Data 2 AXI gpio 3-state (1)R/W0x0 Global Interrupt Enable IER(1)R/W0x0IP Interrupt Enable Register (IP IER).0x0120IP ISR(1)R/TOW(2)0x0IP Interrupt Status : 1. Interrupt registers are available only if AXI gpio is compiled using the Enable Interrupt Toggle-On-Write (TOW) access toggles the status of the bit when a value of 1 is written to the corresponding Address Space Offset is relative to C_BASEADDR 2-5:AXI Parameter-Register DependencyParametersRegister RetainabilityGPIO_DATAGPIO_TRIGPIO2_DATA GPIO2_TRIGIER,IP IER,IP ISRE nable Dual Channel0 YesYesNoNoNA1 YesYesYesYesNAEnable Interrupt0 NANo1 NAYesSend FeedbackAXI gpio October 5, 2: product SpecificationAXI gpio Data Register (GPIOx_DATA)The AXI gpio data register is used to read the general purpose input ports and write to the general purpose output ports.

10 When a port is configured as input, writing to the AXI gpio data register has no are two gpio data registers (GPIO_DATA and GPIO2_DATA), one corresponding to each channel. The channel 1 data register (GPIO_DATA) is always present; the channel 2 data register (GPIO2_DATA) is present only if the core is configured for dual channel (Enable Dual Channel = 1).The AXI gpio Data Register is shown in Figure 2-1, and Table 2-6 details the functionality of this Target - Figure 2-1 Figure 2-1:AXI gpio Data Register0C_GPIOx_WIDTH-1 GPIOx_DATAT able 2-6:AXI gpio Data Register DescriptionBitsField NameAccess TypeReset ValueDescription[GPIOx_Width-1 :0]GPIOx_DATA Read/WriteGPIO: Default Output ValueGPIO2: Default Output ValueAXI gpio Data each I/O bit programmed as input: R: Reads value on the input pin. W: No each I/O bit programmed as output: R: Reads to these bits always return zeros W: Writes value to the corresponding AXI gpio data register bit and output FeedbackAXI gpio October 5, 2: product SpecificationAXI gpio 3-State Control Register (GPIOx_TRI)The AXI gpio 3-state control register is used to configure the ports dynamically as input or output.