Baker Ch. 18 Special Purpose CMOS Circuits …

1 Introduction to VLSIJ oseph A. Elias, Adjunct Professor, University of Kentucky; Modeling Principal, Cypress Semiconductor1 Baker Ch. 18 special purpose cmos circuits Chapter 18 special purpose cmos circuits Schmitt Trigger Mutlivibrator Circuits Monostable Astable Input Buffers Differential DC Reference Reducing Buffer Input Resistance Charge Pumps Dickson PumpIntroduction to VLSIJ oseph A. Elias, Adjunct Professor, University of Kentucky; Modeling Principal, Cypress Semiconductor2 Baker Ch. 18 special purpose cmos circuits Schmitt Trigger DESCRIPTION OUTPUT=L WHEN INPUT > VSPH OUTPUT=H WHEN INPUT < VSPL HYSTERESIS: VH= VSPH VSPL START ANALYSIS WITH OUTPUT OUTPUT=L: M6 ON, M3 OFF, PCHANNEL CKT OUTPUT=H: M3 ON, M6 OFF, NCHANNEL CKTHYSTERESIS0X1X10 Introduction to VLSIJ oseph A. Elias, Adjunct Professor, University of Kentucky; Modeling Principal, Cypress Semiconductor3 Baker Ch. 18 special purpose cmos circuits Schmitt Trigger CALCULATING VSPH OUT=1, 0< VIN<Vtn1 M3 ON, M1, M2 OFF, M3 S=VDD-Vtn3 VIN Vtn M1 ON, M1 S 0 VIN> Vtn AS M1 D 0, VGS>Vtn, M2 ON AS M2 ON, OUT 0, M3 OFF VIN= VSPH= VTN2+ VX CURRENT IN M1, M3 EQUAL SOURCES SAME M2, M3 VTN2=VTN3 1/2 (VSPH-VTN1)2= 3/2 (VDD-VX-VTN3)2 1/ 2= (W1L3)/(L1W3) = [ {VDD - VSPH} / {VSPH- VTN} ]2IN<VtnXX1Vx = VDD-Vtn3IN~VtnX1Vx = VDD-Vtn3 GNDIN>Vtn1 0Vx = GND1 GNDXI ntroduction to VLSIJ oseph A.

2 Elias, Adjunct Professor, University of Kentucky; Modeling Principal, Cypress Semiconductor4 Baker Ch. 18 special purpose cmos circuits Schmitt Trigger APPLICATIONS SMOOTH A RINGING PULSE COMMON IN POWER BUSSES BASIC RING OSCILLATOR fosc= 1 / ( t1+ t2) t1 = RC ln( VSPH/ VSPL) [DISCH] t2 = RC ln( VDD-VSPL/ VDD-VSPL) [CHG] CAP IS INTERNAL AND EXTERNAL VCO RING OSCILLATOR M1, M4 CURRENT SOURCES (M5/6) t1 = C ( VSPH- VSPL) / ID1[DISCH] t2 = C ( VSPH- VSPL) / ID4[CHG]00X11 XVC<VSPHVC>VSPH VSPL11 0 Introduction to VLSIJ oseph A. Elias, Adjunct Professor, University of Kentucky; Modeling Principal, Cypress Semiconductor5 Baker Ch. 18 special purpose cmos circuits CHARGE PUMPS DESCRIPTION VOLTAGE PUMP AKA CHARGE PUMP M1, M2 ACT AS DIODES NODE A DRIVEN TO VDD-Vtn CLOADCHARGED BY C1 OSC=VDD NODE A = VDD-Vtn OSC=GND C1 GND NODE RISES TO VDD NODE A RISES TO VDD+(VDD-Vtn) M2 SOURCE = 2(VDD-Vtn) IDEAL C1>>CLOAD NO RAMP UP OSC f SLOW ENOUGH TO CHG CAP PRACTICAL C1~CLOAD RAMP UP TIME NEEDED OUTPUT DEPENDENT ON DC LOAD VOLTAGE DROOP, VARY W/L, CAPVDDGNDVDD-VtnGNDVDDVDD+VDD-VtnFLTX2 VDD-2 VtnNODE AOUTPUTI ntroduction to VLSIJ oseph A.

3 Elias, Adjunct Professor, University of Kentucky; Modeling Principal, Cypress Semiconductor6 Baker Ch. 18 special purpose cmos circuits CHARGE PUMPS NEGATIVE VOLTAGES NEEDED FOR FN EE, ETC. USE PMOS INSTEAD OF NMOS MAKE SURE NO FB DIODE TO GND IF NWELL TIED TO SOURCE, FB IF NWELL=VDD, BODY EFFECTGNDNWELLDSTVout<GND< GNDN-P-GNDDTVout<GNDGNDN-P-GNDXSGNDDTVout<GNDVDDN-P-GNDXVDDSXXI ntroduction to VLSIJ oseph A. Elias, Adjunct Professor, University of Kentucky; Modeling Principal, Cypress Semiconductor7 Baker Ch. 18 special purpose cmos circuits CHARGE PUMPS MOSFET CAPS VGS>Vtn FOR ALL CONDITIONS STRONG INVERSION CAP CONSTANT VS. BIAS SUBSTRATE RES IF IN ACCUM INCREASING VOUT REMOVE VT DROP VOUT = 2 VDD Vtn A=GND, C=VDD-Vtn A=VDD, C=2 VDD-Vtn VGS>Vtn M4, M5, M6 D=E=VDD (NOT OBVIOUS) A=GND, B=VDD D=E=2 VDD (MOVING REF POINT) VOUT=2 VDD-Vtn M2, M3 ONLY FOR DC LOAD NOT OBVIOUS HOW THIS WORKSGND VDD GNDVDD-Vtn 2 VDD-Vtn ?VDD 0 VDD? VDD 2 VDD? VDD 2 VDDI ntroduction to VLSIJ oseph A.

4 Elias, Adjunct Professor, University of Kentucky; Modeling Principal, Cypress Semiconductor8 Baker Ch. 18 special purpose cmos circuits CHARGE PUMPS DICKSON CHARGE PUMP ARBITRARY LARGE VOLTAGES LIMITED BY OXIDE ASSUME NO DC LOAD CLK=L, A=VDD-Vtn, M2 OFF CLK=H, A=2 VDD-Vtn, M2 ON B=2 VDD-Vtn CLK=L, B=3 VDD-Vtn, M3 ON VOUT N VDD N Vtn (HIGH SIDE) N VDD [(N+1) Vtn] (LOW SIDE) Cn LARGE REDUCES RIPPLEGNDVDD-VtnVDDXVDD2 VDD-VtnGND2 VDD-2 VtnGNDVDD3 VDD-2 VtnIntroduction to VLSIJ oseph A. Elias, Adjunct Professor, University of Kentucky; Modeling Principal, Cypress Semiconductor9 Baker Ch. 18 special purpose cmos circuits CHARGE PUMPS PULSED OUTPUT NMOS PASS GATES, VDD+Vtn IN=0, B~VDD, A~2 VDD ASSUME A=2 VDD-Vtn AS LAST PUMP ASSUME B=VDD-Vtn AS LAST PUMP M1 IS OFF, M2 IS ON M1 VGS=(VDD-Vtn)-(2 VDD-Vtn)=-VDD M2 VGS=(2 VDD-Vtn)-(VDD-Vtn)=VDD IN=1, B~2 VDD, A~VDD ASSUME B=2 VDD-Vtn AS LAST PUMP ASSUME A=VDD-Vtn AS LAST PUMP M2 IS OFF, M1 IS ON M1 VGS=(VDD-Vtn)-(2 VDD-Vtn)=-VDD M2 VGS=(2 VDD-Vtn)-(VDD-Vtn)=VDD VOUT~2 VDD NODE A DOES NOT SUPPLY POWER ONLY NEEDED TO TURN ON M2 SMALL W/L, SMALL CAP NODE B SUPPLIES POWER TO OUT LARGER W/L, LARGER CAP TYPO IN BOOK010~VDD~2 VDDX10101~2 VDD~VDDX0~2 VDDXXI ntroduction to VLSIJ oseph A.

5 Elias, Adjunct Professor, University of Kentucky; Modeling Principal, Cypress Semiconductor10 Baker Ch. 18 special purpose cmos circuits CHARGE PUMPS SUBSTRATE PUMP MAKE SUBSTRATE GO BELOW GND BENEFITS VARY N-CH THRESHOLDS REDUCES LATCHUP PREVENTS FB ON N+ / P- DIODES INPUTS CAN GO NEGATIVE SUBSTRATE ALWAYS <=GND BOOK INDICATES OTHER ITEMS SOME QUESTIONABLE NO LOAD CAP, AS SUB IS A CAP NEED REGULATOR TURNS ON/OFF CLOCK & PUMP SOURCE TO GATE VOLT CONST P-CH FETS ELIMINATES BODY EFF M1, M2 SHIFTS VBB TO VREF NMB PMOS, CONST I SETS VBB SIMPLER REGULATOR LESS ACCURATE M1/2 INV, WITH SW POINT ~Vtn M4 CONST CURRENT SOURCE M5/6 LEVEL SHIFTER0 11 0Vt Vt-VDD? 2Vt-VDDGNDDETERMINESAMOUNT OFRIPPLEPMOSVSG=KCURRENTSOURCELEVELSHIFT ERVtn0-Vt