Board Design Guidelines for PCI Express™ Architecture

1 Board Design Guidelines for PCI Express Architecture Zale Schoenborn Co-Chair, PCI Express Electrical WG. Copyright 2004, PCI-SIG, All Rights Reserved 1. Agenda Background Layout considerations System Board requirements Add-in card designs Signal validations Summary PCI-SIG APAC Developers Conference Copyright 2004, PCI-SIG, All Rights Reserved 2. Background T/s Bus Topology Evolution 133. M. CONN. CONN. MCH. PCI common clock Meet setup/hold timing CLK. Multi-drop parallel I/O T/s M. 533. AGP source synchronous CONN. Single strobe, multiple data MCH. Match all data to strobes T/s PCI Express serial differential +G. Embedded clock CONN.

2 MCH. Point-to-point, match per data pair only Longer route, creative device placement PCI. PCI Express Express pt-to-pt pt-to-pt routing routing is is straightforward straightforward PCI-SIG APAC Developers Conference Copyright 2004, PCI-SIG, All Rights Reserved 3. Background Serial Differential Diff pairs System Board Add-in card AC coupled D+ Lane-to-lane PCI Express Connector RX D- TX de-skew AC caps Polarity TX RX. RX inversion Transmitter & Receiver & On-chip package package equalization (de-emphasis). On-chip TX Spec Interconnect RX terminations Loss < dB. Eye Jitter < UI Spec 175 mV. 800 mV. UI UI. UI = Unit Interval = 400ps (TX eye shown without de-emphasis).

3 PCI-SIG APAC Developers Conference Copyright 2004, PCI-SIG, All Rights Reserved 4. Background PCI Express Routing Trace length matching between pairs is not required Embedded clock simplifies routing rules Longer motherboard traces 12+ inches possible TX pairs usually route on top layer AC coupling caps on TX traces on system Board AC Coupling Caps PCI Express x16 Connector Trace Serpentines Not Required PCI-SIG APAC Developers Conference Copyright 2004, PCI-SIG, All Rights Reserved 5. Background Interconnect Budget Loss and jitter are key parameters Target impedance not as critical Maintain differential pair symmetry Design tradeoffs: loss vs.

4 Trace length, etc. Recommended Solution Space: Graphics Add-In Card System Board traces: Graphics Engine Via Up to 12 inches Manufacturing Probe Point Add-in card traces: AC-Coupling Caps Up to inches GMCH. Chip-to-chip routes: Top System Board traces: Vcc Gnd Bottom Up to 15 inches Manufacturing Probe Point Via X16 Connector Manage Manage loss loss and and jitter jitter to to meet meet budget budget PCI-SIG APAC Developers Conference Copyright 2004, PCI-SIG, All Rights Reserved 6. Layout considerations Stackup Design No new PCB. technology required Standard 4-layer stackup . thick PCB. T. Microstrip oz Cu plated -OR- Stripline 1 oz Cu T = ~62 mils (6+ layers).

5 Follow Follow simple simple layout layout rules rules &. & Design Design tradeoffs tradeoffs PCI-SIG APAC Developers Conference Copyright 2004, PCI-SIG, All Rights Reserved 7. Layout considerations Trace Geometry & Impedance Wide pair-to-pair spacing minimize crosstalk Close intra-pair spacing Same geometry for interleaved/non-interleaved Example impedance targets: Single-end Zo of 60 15%. Differential Impedance of ~100 20%. Tx Tx Tx w Tx Tx 5 7 5 20 mil h Non-interleaved topology example Microstrip Tx Tx Rx w Tx Rx 5 5 5 20 mil h Interleaved topology example Stripline PCI-SIG APAC Developers Conference Copyright 2004, PCI-SIG, All Rights Reserved 8.

6 Layout considerations FR4 Loss Considerations Stackup: FR4 material Glass Material Narrow traces loss Resin Material Copper roughness loss . Dielectrics with more resin material loss . Non-homogeneous dielectrics Localized Zo variation due to material weave loss FR4 cross-section Wide differential impedance variation on strip traces Etching and plating process loss . PCI-SIG APAC Developers Conference Copyright 2004, PCI-SIG, All Rights Reserved 9. Layout considerations Trace Length Longer trace length loss . ~ to dB inherent loss per inch for FR4. microstrip traces at Manage trace lengths to minimize loss Example: 12 Board , add-in card lengths freq 20-inch line dB Example VNA measurements for differential strip trace insertion loss PCI-SIG APAC Developers Conference Copyright 2004, PCI-SIG, All Rights Reserved 10.

7 Layout considerations Trace Symmetry & Matching No matching needed pair-to-pair Match each differential pair per segment Match overall length 5 mils (recommended). Symmetric routing for each pair Preferred matching Match near 45 mils mismatch Alternative matching PCI-SIG APAC Developers Conference Copyright 2004, PCI-SIG, All Rights Reserved 11. Layout considerations Bends and Small Serpentines Avoid tight bends No 90 bends; impact to loss and jitter budgets Keep angles >= 135 (a) C. A. Maintain adequate air gap A >= 4x the trace width B. Lengths of B, C >= the width of the trace >3w w Serpentines length is at least S S1 < 2 S.

8 3w for jog PCI-SIG APAC Developers Conference Copyright 2004, PCI-SIG, All Rights Reserved 12. Layout considerations Package Pin Field Breakout Use side-by-side breakout for package to maintain symmetry Avoid tight bends Side-by-side Best Adjacent w/ small serpentine OK. Adjacent w/ bend Fair Diagonal routing Fair PCI-SIG APAC Developers Conference Copyright 2004, PCI-SIG, All Rights Reserved 13. Layout considerations Reference Plane Full GND plane reference Gnd stitching via recommended Stitching vias required for layer transition Plane Void Keep clearance from Long trace routes plane voids Avoid plane splits Avoid trace over anti-pad PCI-SIG APAC Developers Conference Copyright 2004, PCI-SIG, All Rights Reserved 14.

9 Layout considerations AC Coupling Caps Size: 0402 best, 0603 ok No 0805 size or C-packs Symmetric placement best Cap size: best Same sizes for both D+/D- Cap location: Along Tx pairs on system Board Along Tx pairs on add-in card PCI-SIG APAC Developers Conference Copyright 2004, PCI-SIG, All Rights Reserved 15. Layout considerations Test Points & Vias Minimize via usage Up to dB loss per via Use via pad size 25 mil, hole size 14 mil; standard anti-pad size of 35 mil Put test points or LAI pads in series (if used). No stubs Place symmetrically Provide GND pads for single-ended probing LAI pads Probe pads GND pads PCI-SIG APAC Developers Conference Copyright 2004, PCI-SIG, All Rights Reserved 16.

10 System Board requirements Reference Clock Clocks have no phase relationships Length matching for clocks is NOT required! Deliver diff clock to each device and connector Use same trace geometries as other diff pairs Clock driver requirements: 100 MHz with SSC support ( CK410). System Board (source) termination only Rise/fall slew rate requirements need to be met . Clock Driver 22 - 33 . Rs 5% 1 14 PCI Express PCI Express Card Connector L1 L2 L4 L5. L1' L2' L4' L5'. Rs 0 . max L3' L3. 0 . Rt Rt 1%. PCI-SIG APAC Developers Conference Copyright 2004, PCI-SIG, All Rights Reserved 17. System Board requirements Connector Layout Side B: Side A: Connector with standard PTH Tx Rx Connector sizes: x1, x4, x8, x16.