Chapter 3 Basic MOSFET logic gates

1 Chapter 3 Basic MOSFET logic InverterWhen building digital gates out of mosfets , we will be observing three Basic rules:1. Only use NFETs to pull the output down and PFETs to pull the output Never allow the output to be simultaneously pulled up and Always ensure that the output is either pulled-up or pulled-down, so that the output state isalways simplest, non-trivial logic gate that satisfies rule 1 is the logic gate composed of a singleNFET (to pull the output down) and a single PFET (to pull the output up). This arrangement wasalready described in Figure However, the configuration of Figure (e) violates rule 2 and theconfiguration of Figure (d) violates rule 3. Hence only the configurations of Figures (b) and(c) satisfy all three Basic note that for the two valid configurations, both MOSFET gates must be at the same we can connect these two MOSFET gates and call that the input to our logic gate . Further-more, we note that when this input is 1 (Vdd) the output is 0 (Gnd), and when this input is 0 (Gnd)the output is 1 (Vdd).

2 Hence the logic gate that we have constructed is an inverter. This logic gateand its operation is summarized in Figure (a)DQQ dX(b)dDX!r r(c)D=X(d)Figure : Inverter. (a) Truth table. (b) Symbol. (c) Schematic. (d) Boolean NAND gatesThe next simplest gate is the two input NAND gate , shown in Figure This gate is composedof two NFETs in series to pull the output low, and two PFETs in parallel to pull the output high,which satisfies rule (a)D%$XYdD(b) d!d!rr rrXYD(c)(d)D=X YFigure : Two input NAND. (a) Truth table. (b) Symbol. (c) Schematic. (d) Boolean operation of the two input NAND gate is as follows. When theXandYinputs are bothhigh, the two NFETs turn on and pull the output low. At this point, the two PFETs are both off, soneither is pulling the output high and rule 2 is eitherXorYis low, then at least one of the NFETs will turn off, preventing the output frombeing pulled low. Simultaneously, at least one of the PFETs will turn on and pull the output high,satisfying rule two input NAND gate can be extended to three inputs by placing three NFETs in series andthree PFETs in parallel as in Figure The operation is the same as for the two input NAND gate ,satisfying all three Basic rules.

3 Continuing the process, the NAND gate can be further extended tomore three inputs as (a)11111101010101010011001100001111%$dD( b)XYZ(c)!drX!d!drDrr rYZ(d)D=X Y ZFigure : Three input NAND. (a) Truth table. (b) Symbol. (c) Schematic. (d) Boolean NOR gatesIf we take the two input NAND gate and place the NFETs in parallel and the PFETs in series, weget a NOR gate as shown in Figure gate still uses PFETs to pull the output high and NFETs to pull the output low, satisfyingrule 1. In operation, when theXandYinputs are low, the two PFETs turn on and pull the outputhigh, and both NFETs are off so that rule 2 is satisfied. When eitherXorYis high, then one of thePFETs will turn off, preventing the output from being pulled high, and one of the NFETs will turnon and pull the output low, so that rule 3 is (a)dD(b)XYDdd rrXrr!D (c)Y(d)D=X+YFigure : Two input NOR. (a) Truth table. (b) Symbol. (c) Schematic. (d) Boolean MultiplexorFigure shows the truth table, symbol, schematic and Boolean expression for a two input (a)10 XYQQdD(b) S(c)dddd!

4 !r rDYXYXSSSS(d)D=X S+Y SFigure : Two input multiplexor. (a) Truth table. (b) Symbol. (c) Schematic. (d) operation of the multiplexor is as follows. WhenSis low, the PFET controlled bySandthe NFET controlled bySare turned off, preventingYfrom affecting the outputD. However, the15 PFET controlled bySand the NFET controlled bySare turned on, which allowsXto control thestate of the outputD. Hence, whenXis low,Dwill be pulled high, and whenXis high,Dwill bepulled , whenSis high, the PFET controlled bySand the NFET controlled bySare turnedoff, preventingXfrom affecting the outputD. However, the PFET controlled bySand the NFET controlled bySare turned on, which now allowsYto control the state of the outputD. Hence,whenYis low,Dwill be pulled high, and whenYis high,Dwill be pulled 4 Constructing custom logic Truth table methodAlthough we can construct any digital system using only the two input NAND gate , this wouldresult in a circuit that is innefficient in space, speed and construct a custom logic gate , the simplest method is to start with the truth table, and con-struct one branch for each line in the truth table.

5 Given anninput truth table, each branch willbe constructed ofnseries PFETs ornseries NFETs depending on whether the output for thecorresponding line in the truth table is a 1 or a instance, suppose that we have the truth table shown in Figure (a). For line 0, we wantthe output to be low, so we select two series connected NFETs. In order for these two NFETs tobe on simultaneously for the input state of line 0 (XandYare both low), we need to connect thegates of the NFETs toXandY. This configuration is shown in Figure (b). Similarly, for line 3,we also need NFETs, but this time the gates will be connected toXandY. This configuration isshown in Figure (e).Line 0 Line 1 Line 2 Line 3011001000111Y X D(a)D(b)YXdd!D(c)YXdd!D(d)XYD(e)YXFigure : Two input XOR. (a) Truth table. (b) NFET branch for line 0. (c) PFET brach for line1. (d) PFET branch for line 2. (e) NFET branch for line lines 1 and 2, we want the output to be high, so we select two series connected PFETs.

6 Toturn these PFETs on for their respective input states, one pair will be connected toXandY(line 2)and the other will be connected toXandY. These two configurations are shown in Figures (c)and (d). The end result is shown in Figure a truth table withninputs has2nlines, this method will result in a circuit that has2nbranches ofnMOSFETs each, orn2ntotal (a)D(b)XYP(c)dddd!!r rDXXXXYYYY(d)D=X YFigure : Two input XOR. (a) Truth table. (b) Symbol. (c) Schematic. (d) Boolean gates can also be constructed from truth tables using parallel branches of NFETs orPFETs. To do this, we design branches to block the pull up or pull down action. For instancefor the XOR used in the previous example, line 0 would convert to two parallel PFETs with gatesconnected toXandY. This would prevent the output from being pulled high branches composed of parallel mosfets results in gates which have the same numberof transistors as using branches composed of series mosfets .

7 However, experience shows thatusing parallel mosfets results in larger and slower logic gates , and for these reasons, logic gatesare rarely constructed this Complementary structures methodSuppose that we use the previous method to construct a NAND gate . The resulting circuit wouldlook like the one shown in Figure Comparing Figures (b) and (b) it is evident thatthe truth table method can result in an implementation with an excessive number of , implementation of Figure (b) uses the complements of the input signalsXandY, which themselves require inverters to generate from the original input signals. Although it ispossible to reduce the circuit of Figure (b) to that of Figure (b), it is generally difficult to , we note that the pull down branch which corresponds to line 3 of the truth table isthe same in both instances. The complementary structures method takes advantage of this to formthe pull up network of PFETs from the pull down network of NFETs (orvice versa).

8 With the complementary structures method, we replace NFETs with PFETs (or PFETs withNFETs), parallel branches with series branches and series branches with parallel branches. Thesignals going to the gates of the mosfets remain example, the PFET branch shown in Figure (b) is the complement of the NFET branchshown in Figure (a). The PFET branch was created by converting the parallel NFETs controlledbyXandYinto the series PFETs also controlled byXandY. The NFET controlled byZwasin series with the NFETs controlled byXandY, hence the PFET controlled byZgoes in parallel18(a)Line 3 Line 2 Line 1 Line 0111001010011 DXY2irX!dd!dd!dXdDr0i i13i(b)YYXXYYF igure : Two input NAND implemented with truth table method. (a) Truth table. (b) the PFETs controlled byXandY. Combining these two complementary structures producesthe OR-NAND shown in Figure (a)rXrYZddXYdZrr(b)Figure : Two complementary structures. (a) NFET branch. (b) PFET Boolean equation methodThe reason that the complementary structures method works is that any network of NFETs (orPFETs) can be reduced to a single NFET (or PFET) with a Boolean expression attached to thecontrol Basic conversion possibilities are shown in Figure The use of this method is demon-strated in Figures and with the pull down network of Figure (a), we take the two series NFETs con-nected toXandYand convert them to a single NFET connected toX+Yas shown in Fig-ure (b).

9 Now we have two NFETs in parallel, and we convert them to a single NFET connectedto(X+Y) Zas shown in Figure (c).Given a single NFET pull down, we know that we need only a single PFET pull up with thesame gate control signal as in an inverter. Hence the pull up PFET that we need in conjunctionwith the pull down NFET of Figure (c) is the PFET shown in Figure (a).1911111000001100110101010100001111 DXYZ(a)ZYX(b)D$%dDrr!drdd!DXYXZZY(c)(d)D =(X+Y) ZFigure : OR-NAND. (a) Truth table. (b) Symbol. (c) Schematic. (d) Boolean X YdddXY X+YdYX X YrrXY X+YFigure : Boolean equivalent we can proceed with the reverse process and reexpand the circuit, as shown in Fig-ures (b) and (c). The complete logic gate is shown in Figure , and is indeed an AND-NORgate as expected given the Boolean intermediate (a)rZrX Y(b)(X Y) +Z(c)Figure : Boolean equivalent circuit (a)(X Y) +ZddZX Y(b)dXrdYrdZ(c)Figure : Boolean equivalent circuit (a)DXYZZYX(b)$DdD%!

10 D!(c)rDddrrXYZXYZ(d)D=(X Y) +ZFigure : AND-NOR. (a) Truth table. (b) Symbol. (c) Schematic. (d) Boolean