Chapter 6 Synchronous Sequential Circuits

1 Chapter 6 Synchronous Sequential Circuits In a combinational circuit , the values of the outputs are determined solely by the present values of its a Sequential circuit , the values of the outputs depend on the past behavior of the circuit , as well as the present values of its Sequential circuit has states, which in conjunction with the present values of inputs determine its Circuits can be: ! Synchronous where flip-flops are used to implement the states, and a clock signal is used to control the operation ! Asynchronous where no clock is used Figure The general form of a Synchronous Sequential circuit Flip-flopsClock Q W Z Combinational circuit If the outputs depend only on the present state, the circuit is said to be of Moore the outputs depend on both the present state and the present values of the inputs, the circuit is said to be of Mealy Sequences of input and output : t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10w : 0 1 0 1 1 0 1 1 1 0 1 z.

2 0 0 0 0 0 1 0 0 1 1 0 Figure State diagram of a simple Sequential z 1 = Reset B z 0 = A z 0 = w 0 = w 1 = w 1 = w 0 = w 0 = w 1 = Figure State table for the Sequential circuit in Figure Next state Outputstate w = 0 w = 1 z A A B 0 B A C 0 C A C 1 Figure A general Sequential circuit with input w, output z, and two state present state variables, y1 and y2, determine the present state of the next state variables, Y1 and Y2, determine the state into which the circuit will go after the next active edge of the clock State-assigned table for the Sequential circuit in Figure Next state state w = 0 w = 1 Outputy 2 y 1 Y 2 Y 1 Y 2 Y 1 z A 0000010 B 0100100 C 1000101 11ddddd Figure Derivation of logic expressions for the Sequential circuit in Figure 000111100 1 0 1 0 y 2 y 1 Y 1 wy1 y 2 = w 000111100 1 0 d 1 d y 2 y 1 Y 2 wy1 y 2 wy1 y 2 + = d d 0 0 0 0 0 0 1 0 1 0 1 0 d y 1 z y 1 y 2 = 0 1 y 2 Y 1 wy1 y 2 = Y 2 wy1 wy2 + = z y 2 = w y 1 y 2 + ( ) = Ignoring don't caresUsing don't cares Figure Final implementation of the Sequential circuit derived in Figure Timing diagram for the circuit in Figure 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 101 0 1 0 1 0 1 0 Clock w y 1 y 2 1 0 z Design the specification of the desired circuit .

3 A state diagram. the corresponding state table. the number of states if possible. on the number of state variables. the type of flip-flops to be used. the logic expressions needed to implement the System for Example State diagram for Example R 3 out 1 = R 1 in1 = Done1 = , , w 0 = w 1 = C R 1 out 1 = R 2 in1 = , B R 2 out 1 = R 3 in1 = , w 1 = A No w 0 = w 1 = transferw 0 = w 1 = Reset w 0 = Figure State table for Example Next state Outputs state A A B 0 0 0 0 0 0 0 B C C 0 0 1 0 0 1 0 C D D 1 0 0 1 0 0 0 D A A 0 1 0 0 1 0 1 w = 0 w = 1 Figure State-assigned table for the Sequential circuit in Figure Next state state Outputs A 00000 1 0 0 0 0 0 0 0 B 01101 0 0 0 1 0 0 1 0 C 10111 1 1 0 0 1 0 0 0 D 11000 0 0 1 0 0 1 0 1 Figure Derivation of next-state expressions for the Sequential circuit in Figure 000111100 1 1 1 1 y 2 y 1 Y 1 wy1 y 1 y 2 + = w 000111100 1 1 1 1 1 y 2 y 1 Y 2 y 1 y 2 y 1 y 2 + = Figure Final implementation of Sequential circuit in Figure Improved state assignment for the Sequential circuit in Figure Next state state w = 0 w = 1 Outputy 2 y 1 Y 2 Y 1 Y 2 Y 1 z A 0000010 B 0100110 C 1100111 10ddddd Figure Final circuit for the improved state assignment in Figure Q Q D Q Q Y 2 Y 1 w Clock z y 1 y 2

4 ResetnFigure Improved state assignment for the Sequential circuit in Figure Nextstate state Outputs A 000 0 010 0 0 0 0 0 0 B 011 1 110 0 1 0 0 1 0 C 111 0 101 0 0 1 0 0 0 D 100 0 000 1 0 0 1 0 1 Figure Derivation of next-state expressions for the Sequential circuit in Figure 000111100 1 1 1 1 y 2 y 1 Y 1 wy2 y 1 y 2 + = w 000111100 1 1 1 1 1 y 2 y 1 Y 2 y 1 = Figure One-hot state assignment for the Sequential circuit in Figure Nextstate state w = 0 w = 1 Outputy 3 y 2 y 1 Y 3 Y 2 Y 1 Y 3 Y 2 Y 1 z A 001 001 010 0 B 010 001 100 0 C 100 001 100 1 Figure One-hot state assignment for the Sequential circuit in Figure Present Nextstate state Outputs A 0 001 000100100 0 0 0 0 0 0 B 0 010 010001000 0 1 0 0 1 0 C 0 100 100010001 0 0 1 0 0 0 D 1 000 000100010 1 0 0 1 0 1 Figure Sequences of input and output signals. Clock cycle: t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 1 0 0 1 1 0 0 Figure State diagram of an FSM that realizes the task in Figure w 0 = z 0 = w 1 = z 1 = B w 0 = z 0 = Reset w 1 = z 0 = Figure State table for the FSM in Figure Next state Outputz state w = 0 w = 1 w = 0 w = 1 A A B 0 0 B A B 0 1 Figure State-assigned table for the FSM in Figure Next state Outputstate w = 0 w = 1 w = 0 w = 1 y Y Y z z A 0 0 1 0 0 B 1 0 1 0 1 Figure Implementation of FSM in Figure ResetnD Q Q w z (a) circuit t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 101 0 1 0 1 0 1 0 Clock y w z y (b) Timing diagramFigure circuit that implements the specification in Figure State diagram for Example ,,w0=w1=R1out1=R2in1=,w1=R 2out1=R3in1=,Aw0=w1=Resetw0=BCFigure Verilog code for the FSM in Figure simple (Clock, Resetn, w, z); input Clock, Resetn, w; output z; reg [2:1] y, Y.

5 Parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10; // Define the next state combinational circuit always @(w, y) case (y) A: if (w) Y = B; else Y = A; B: if (w) Y = C; else Y = A; C: if (w) Y = C; else Y = A; default: Y = 2'bxx; endcase // Define the Sequential block always @(negedge Resetn, posedge Clock) if (Resetn = = 0) y <= A; else y <= Y; // Define output assign z = (y = = C); endmoduleFigure Implementation of the FSM of Figure in a see portrait orientation PowerPoint file for Chapter 6 Figure The circuit from Figure in a small z Resetnw Clock Gnd V DD1 4 7 10131619222528443936 Figure Simulation results for the circuit in Figure Second version of code for the FSM in Figure simple (Clock, Resetn, w, z); input Clock, Resetn, w; output reg z; reg [2:1] y, Y; parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10; // Define the next state combinational circuit always @(w, y) begin case (y) A: if (w) Y = B; else Y = A; B: if (w) Y = C; else Y = A; C: if (w) Y = C; else Y = A; default: Y = 2'bxx.

6 Endcase z = (y = = C); //Define output end // Define the Sequential block always @(negedge Resetn, posedge Clock) if (Resetn = = 0) y <= A; else y <= Y; endmoduleFigure Third version of code for the FSM in Figure simple (Clock, Resetn, w, z); input Clock, Resetn, w; output z; reg [2:1] y; parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10; // Define the Sequential block always @(negedge Resetn, posedge Clock) if (Resetn = = 0) y <= A; else case (y) A: if (w) y <= B; else y <= A; B: if (w) y <= C; else y <= A; C: if (w) y <= C; else y <= A; default: y <= 2'bxx; endcase // Define output assign z = (y = = C).

7 EndmoduleFigure Verilog code for the FSM in Figure see portrait orientation PowerPoint file for Chapter 6 Figure Verilog code for the Mealy machine of Figure see portrait orientation PowerPoint file for Chapter 6 Figure Simulation results for the Mealy Potential problem with asynchronous inputs to a Mealy Block diagram for the serial A B + = Shift registerShift registerAdder FSM Shift registerB A a b s Clock Figure State diagram for the serial adder 001 111 100 010 H 101 011 000 carry-in0 = carry-in1 = G:H:Reset 110 abs ( ) Figure State table for the serial adder Next state Outputs state ab=00 01101100011011G G G G H 0 1 1 0 H G H H H 1 0 0 1 Figure State-assigned table for Figure Next state Outputstate ab=00 01101100011011y Y s 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 1 Figure circuit for the adder FSM in Figure State diagram for the Moore-type serial adder 1 s 1 = Reset H 0 s 0 = 011011110110G 1 s 1 = G 0 s 0 = 01100001001011000011 Figure State table for the Moore-type serial adder Nextstate Outputstate ab=00 011011s G 0 G 0 G 1 G 1 H 0 0 G 1 G 0 G 1 G 1 H 0 1 H 0 G 1 H 0 H 0 H 1 0 H 1 G 1 H 0 H 0 H 1 1 Figure State-assigned table for Figure Nextstate state ab=00 011011 Outputy 2 y 1 Y 2 Y 1 s 000 0 010 1 100 010 0 010 1 101 100 1 101 0 110 110 1 101 0 111 Figure circuit for the Moore-type serial adder a b D Q Q Carry-out Clock Reset D Q Q s Y 2 Y 1 Sum bit y 2 y 1 Figure Code for a left-to-right shift register with an enable

8 Shiftrne (R, L, E, w, Clock, Q); parameter n = 8; input [n-1:0] R; input L, E, w, Clock; output reg [n-1:0] Q; integer k; always @(posedge Clock) if (L) Q <= R; else if (E) begin for (k = n-1; k > 0; k = k-1) Q[k-1] <= Q[k]; Q[n-1] <= w; end endmoduleFigure Verilog code for the serial see portrait orientation PowerPoint file for Chapter 6 Figure Synthesized serial see portrait orientation PowerPoint file for Chapter 6 Equivalence of statesTwo states Si and Sj are said to be equivalent if and only if for every possible input sequence, the same output sequence will be produced regardless of whether Si or Sj is the initial State table for Example Next state Outputstate w = 0 w = 1 z A B C 1 B D F 1 C F E 0 D B G 1 E F C 0 F E D 0 G F G 0 Figure Minimized state table for Example Nextstate Outputstate w = 0 w = 1 z A B C 1 B A F 1 C F C 0 F C A 0 Figure Signals for the vending Q Q sense N D Q Q Clock N sense N sense D Clock N D (a) Timing diagram(b)

9 circuit that generates N Figure State diagram for Example S71 DND N S30 S60 S91 S81 S20 S51 S41 DNDNDNDNDNDNDND D N D N DNN Reset Figure State table for Example Next state Outputstate DN=00 011011z S1S1S3S20 S2S2S4S50 S3S3S6S70 S4S11 S5S31 S6S6S8S90 S7S11 S8S11 S9S31 Figure Minimized state table for Example Next state Outputstate DN=00 011011z S1S1S3S20 S2S2S4S50 S3S3S2S40 S4S11 S5S31 Figure Minimized state diagram for Example S51 DNDNDNDNDND D D N N N S30 S2 0 S41 Figure Mealy-type FSM for Example 0 S1D 1 D 1 N 1 N 0 N 0 DN0 DN0 DN0 Figure Incompletely specified state table for Example Next state Outputz state w = 0 w = 1 w = 0 w = 1 A B C 0 0 B D 0 C F E 0 1 D B G 0 0 E F C 0 1 F E D 0 1 G F 0 Figure State diagram for the State table for the Next state Outputstate w = 0 w = 1 A A B 0 B B C 1 C C D 2 D D E 3 E E F 4 F F G 5 G G H 6 H H A 7 Figure State-assigned table for the Next state state w = 0 w = 1 Count y 2 y 1 y 0 Y 2 Y 1 Y 0 Y 2 Y 1 Y 0 z 2 z 1 z 0 A 000 000 001 000 B 001 001 010 001 C 010 010 011 010 D 011 011 100 011 E 100 100 101 100 F 101 101 110 101 G 110 110 111 110 H 111 111 000 111 Figure Karnaugh maps for D flip-flops for the 0 1 1 1 0 0 0 0 1 0 0 0 1 1 1 1110y 1 y 0 wy2 0001111000010 0 0 1 1 1 1 0 1 0 1 0 0 1 1 0 1110y 1 y 0 wy2 0001111000010 1 1 0 1 0 1 0 1 0 0 0 1 1 0 1 1110y 1 y 0 wy2 Y 2 wy2 y 0 y 2 y 1 y 2 w + + + y 0 y 1 y 2 = Y 0 wy0 wy0 + = Y 1 wy1 y 1 y 0 wy0 y 1 + + = Figure circuit diagram for the counter implemented with D see portrait orientation PowerPoint file for Chapter 6 Figure Excitation table for the counter with JK Flip-flop inputsstate w = 0 w = 1 Count y 2 y 1 y 0 Y 2 Y 1 Y 0 J 2 K 2 J 1 K 1 J 0 K 0 Y 2 Y 1 Y 0 J 2 K 2 J 1 K 1 J 0 K 0 z 2 z 1 z 0 A 000 000 0d0d0d001 0d0d1d000 B 001 001 0d0dd0010

10 0d1dd1001 C 010 010 0dd00d011 0dd01d010 D 011 011 0dd0d0100 1dd1d1011 E 100 100 d00d0d101 d00d1d100 F 101 101 d00dd0110 d01dd1101 G 110 110 d0d00d111 d0d01d110 H 111 111 d0d0d0000 d1d1d1111 Figure Karnaugh maps for JK flip-flops in the see portrait orientation PowerPoint file for Chapter 6 Figure circuit diagram using JK Resetnw J Q Q K y 0 y 1 y 2 J Q Q K J Q Q K Figure Factored-form implementation of the Resetnw y 0 y 1 y 2 J Q Q K J Q Q K J Q Q K Figure State table for the counterlike NextOutputstate state z 2 z 1 z 0 A B 000 B C 100 C D 010 D E 110 E F 001 F G 101 G H 011 H A 111 Figure State-assigned table for Figure NextOutputstate state y 2 y 1 y 0 Y 2 Y 1 Y 0 z 2 z 1 z 0 000 1 000 00100 0 101 00010 1 100 10110 0 011 10001 1 010 01101 0 111 01011 1 110 11111 0 001 11 Figure circuit for Figure Q Q z 0 D Q Q D Q Q z 1 z 2 w Figure State diagram for the 1xx Reset gnt1g 1 1 = x1x gnt2g 2 1 = xx1 gnt3g 3 1 = 0xx 1xx 01x x0x 001 xx0 Figure Alternative style of state diagram for the 1 r 2 r 1 r 2 r 3 IdleReset gnt1g 1 1 = gnt2g 2 1 = gnt3g 3 1 = r 1 r 1 r 1 r 2 r 3 r 2 r 3 r 1 r 2 r 3 Figure Verilog code for the see portrait orientation PowerPoint file for Chapter 6 Figure circuit for Example Q Q D Q Q Clock Resetny 2 y 1 Y 2 Y 1 w z Figure Tables for the circuit in Example Next State state w = 0 w = 1 Outputy 2 y 1 Y 2 Y 1 Y 2 Y 1 z 0 0 0 0 010 0 1 0 0 100 1 0 0 0 110 1 1 0 0 111 (a) State-assigned tablePresent Next state Outputstate w = 0 w = 1 z A A B 0 B A C 0 C A D 0 D A D 1 (b) State t