Clocked and Asynchronous FIFO Characterization and …

1 Clocked and Asynchronous FIFOC haracterization and ComparisonHoSuk HanKenneth S. StevensElectrical and Computer EngineeringUniversity of UtahAbstract Heterogeneous blocks, IP reuse, network-on-chipinterconnect, and multi-frequency design are becoming moreprevalent in integrated circuit design. Communication amongstthese blocks typically employs first-in-first-out ( fifo ) bufferingfor flow control. This paper characterizes and evaluates severalcommon designs in order to determine which structure is bestfor various specific applications. Two Clocked and four clocklessasynchronous fifo designs are compared varying capacity,bit width, and structural configurations. The fifo layoutsare characterized in the IBM 65nm 10sf process for latency,throughput, area, and power. First order models are created toaid in CAD for fifo synthesis, modeling, and optimization. Com-parative results show that the Asynchronous designs uniformlyout perform the Clocked designs in nearly every INTRODUCTIONFIFOs are an increasingly important component as designhas become more modular.

2 The choice of which structuredmemory to employ can have significant impact on the power,performance, and cost of a design. The choices are broad andrange from Clocked to Asynchronous designs [1] [6]. Someexcellent work on the properties of FIFOs has been published[7], [8]. Yet a clear understanding of the comparative cost ofdifferent designs in terms of power, throughput, latency, andarea and of the key differences between specific structures is not generally available. This paper reports on a studyperformed for a two fold purpose: to help designers choose thebest fifo for their target design, and to develop the foundationfor an automatic CAD tool for selecting and synthesizing thebest most common Clocked and Asynchronous designs arecompared across a broad range of design metrics. The designsare characterized for buffering capacity, energy per data word,leakage energy, width of the data path, forward and backwardlatency, throughput for a given occupancy, and area.

3 Many ofthe Asynchronous designs have various structural choices, andthese structures are compared and optimized. First-order equa-tions are that allow designs to be compared across arbitraryparameterized ranges are also work evaluates the most common fifo structures. Twoclocked and four Asynchronous fifo classes are Clocked designs are assumed to operate entirely in asingle clock domain. Synchronization costs are ignored inthis analysis if the Asynchronous design is placed in a clockdomain. No status information beyond full at the write portand empty at the read port is 1. Schematic of the linear pipeline controllerThe end goal is to develop a tool to algorithmically evaluatethe merits of various fifo structures and generate a parame-terized synthesis system that will create the most appropriatedesign. The choice can have significant impact. For instance,the best 8 word Asynchronous fifo expends half the energywith a forward latency that is almost a third that of thebest Clocked fifo while achieving nearly identical maximumthroughput.

4 In general, the Asynchronous designs are shownto significantly out perform Clocked designs for nearly everymetric and across nearly the full range of design DESIGN ANDCHARACTERIZATIONThe results reported in this paper are derived from thelayout of designs that have been automatically synthesized andcharacterized. The designs have been physically placed androuted in the IBM 10sf 65nm process technology using theArtisan RVt 12T library. Simulation results use full parasiticextraction from implementations are designed to achieve the goal ofmaking them as comparable as possible. This is accomplishedby employing the same universal subcomponents to constructboth the Asynchronous and Clocked fifo designs. For in-stance, the same Clocked one-hot shift register is used foraddress selection in the Clocked head / tail pointer designas well as the Asynchronous parallel and rectangular , the same pipeline controller, shown in Fig. 1, is usedin all the Asynchronous design and Characterization flow proceed as , a small set of shared circuit templates were are implemented as a behavioral or structural Verilogmodule.

5 The structural modules are mapped to the Artisan65nm static library. There are 10 separate modules, three ofwhich are Asynchronous state machines, the rest consist of Clocked components. The data registers are composed ofbanks of flip-flops for the Clocked head / tail pointer design,and data latches for all other Asynchronous modules consist of either pipelined stageswhich contain a latch bank to store data, or unpipelinedstages that steer the control and data bits. The asynchronousunpipelined modules consist entirely of Clocked elements,such as the one-hot shift register. The pipelined modules havean Asynchronous state machine that controls the clock signal tothe latch bank that stores the data, and performs flow controlbetween buffer stages. The linear pipeline controller circuitof Fig. 1 is a typical example of an Asynchronous finite statemachine (AFSM) controller. The other Asynchronous AFSM designs include the binary toggle and merge components thatbuffer and steer data between three three Asynchronous finite state machine controllerswere synthesized or hand designed, and implemented asstructural Verilog modules mapped to the static Artisan celllibrary.

6 These circuits used a Characterization flow that permitstheir use in Clocked ASIC CAD flows [9]. This character-ization includes formal verification to prove behavioral andtiming correctness. Constraints are employed to ensure thestructure of the cells are not modified by the CAD tools,but that the drive strengths can be correctly optimized forpower and delay by using theset_size_onlycom-mands for these modules. Specific timing in the asynch-ronous modules not understood by the Clocked CAD aredefined withset_max_delay,set_min_delay, andset_data_checkcommands. Thesesdccommands areused by the logic synthesis and place and route tools. They areemployed in a way that ensures that the Asynchronous designsare power and timing optimized just as the Clocked Clocked templates include a one-hot shift register foraddress generation, a counter, unpipelinedn-way toggle andmerge modules, and an elastic half buffer pipeline controller[10], [11]. Each are implemented as a behavioral or structuralVerilog module depending on the components are assembled together to build the sixFIFO classes reported in this paper.

7 A custom parameterizedscript was written to synthesize the completed fifo architec-tures as Verilog designs. The result of the script is a Verilogregister transfer level (RTL) design. The RTL typically consistsof both structural and behavioral Verilog designs are synthesized using Design Compilerand then physically placed and routed using SoC design area is measured from SoC Encounter and thensimulated for power and performance using Modelsim. Resultsfrom Modelsim import delays calculated from parasitic ex-traction from the physical layout in SoC Encounter using thestandard delay format (sdf). One simulation in Modelsim isdesigned to measure the power. This simulation generates avalue change dump (vcd) file that logs the switching activityon every node in the design. Thevcdfile is imported into SoCwhich generates the power results based on the parasitics andactual activity factors of the nodes from frequency of the Clocked FIFOs is determined bysimulating the design, increasing the clock frequency untilFig.

8 2. Phased Elastic Half Buffer (pEHB) design fails, then backing off the timing by 15%. Thefrequency of the Asynchronous fifo designs are a result ofthe system logic delays and margins designed in the race simulations were performed on each design toevaluate latencies, worst case throughput, and energy undervarious activity factors. A simulation algorithm to ensure a fairenergy comparison was developed by generating patterns thatguaranteed identical activity factors on all transfers betweenstorage elements. Data activity factors ranging from to50% on all data paths were simulated. The designs were alsosimulated across all valid occupancies to generate throughputversus occupancy graphs. Due to the volume of the tests,simulation and Characterization scripts were developed toautomate fifo of different designs were synthesized andcharacterized. Each fifo class, and at times many structuralvariants, were designed with capacities ranging from twothrough 50 words and data path widths ranging from fromzero up to 64 bits.

9 The scripts developed to generate theVerilog fifo designs is therefore highly parameterized. Theparameters include selections to identify (i) one of the sixFIFO classes, (ii) the structural configuration specific to thatclass ( different widths and depths described in Sec. IV),(iii) the capacity of the fifo , and (iv) the width of the datapath. Behavioral test interfaces are attached to the head andtail of the FIFOs to aid in the simulation results are evaluated and first order modelsdeveloped for capacity, throughput, energy scaling, and perfor-mance values. These models can be implemented in a CADtool to automatically select and synthesize the best fifo forspecific design parameters and quality fifo CLASSESTwo Clocked structures are used: linear flow-through FIFOand head / tail pointer. The linear Clocked fifo is imple-mented as phased elastic half buffer cells (Fig. 2) that employlatches for data storage [10], [11]. This logic implements alatency insensitive protocol [12], [13].

10 Elastic half buffersmust be connected where the control and data latches alternatebetween transparent high and low cells in adjacent 3. Design of the Clocked Head/Tail Pointer fifo . Read and write pointers are one-hot shift 4. Block diagram of a 4-deep Linear fifo . L1 L4 are the controllerof Fig. 1, D1 D4 are latch implementation of the Clocked pointer fifo is shownin Fig. 3 [3]. The read and write pointers are implemented witha circular Clocked one-hot shift register for address Asynchronous structures are implemented: linear, par-allel, binary tree, and square [1], [4], [8]. A linear structurewith capacity of four is shown in Fig. 4. All asynchronousFIFOs and the Clocked linear fifo use latches for data structure of Fig. 4 is used in each of the asynchronousdesigns, where the combination of the linear controller andlatch bank form a pipeline stage, just like a DiLipair inFig. 4. A normally closed latching protocol is used forenergy efficiency where the latches are only briefly transparentto store the block diagram of the parallel fifo is shown in Fig.