CMOS DEVICE ARCHITECTURE EVOLUTION AND …

1 CONFIDENTIALCMOS DEVICE ARCHITECTURE EVOLUTION AND metrology CHALLENGESNAOTO HORIGUCHI, IMECCONFIDENTIALOUTLINE CMOS scaling trend and imec DEVICE roadmap DEVICE scaling and metrology challenges FinFET Horizontal nanowire FET Vertical nanowire FET TFET 2D material devices Summary2 CONFIDENTIALCMOS SCALING TRENDTRANSISTOR ARCHITECTURE UNDER PRESSURElog2(#transistors/$)201520132011 2009200714nm20nm28nm40nm65nm90nm20172019 202120232025200510nm7nm5nm7(?)-5nm: Finfet with channel stress and/or Nanowire : Planar DEVICE runs out of steam -electrostatics14nm: Si FinFET DEVICE improved electrostatics, current density, and : Fin/Nanowire devices run out of steamHappy scaling era# transistors per areadoubles every two yearfor same & beyond3D (Vertical) LogicHybrid stackingBeyond CMOSNew compute paradigmsSTCOLess happy scaling eraStill doubles but devicescaling provides diminishing returnsNOWF ocus of process technology innovation isScale DEVICE and wireScale basic logic cellsScale (sub-)system functionsCONFIDENTIALIMEC HIGH PERFORMANCE MOBILE LOGIC ROADMAPE arly fdry production2014N14 (industryref.)

2 (V) or HGAAFinFET or HGAAHGAAC hannel nfet/pfetSi / SiSi / Si {SiGe}Si / SiGeSi/ SiGe(Highermobility)Gate Pitch (nm)70-90, 193i64, 193i42,193i32, EUVTBDGate length (nm)30242018-1414-10 Contact metalWWW or CoAlternativemetalAlternative metalMetal Pitch (nm)52-64, 193i42, 193i32, 193i, EUV cut/Via24, EUV18,EUVLow k + CuTaN/Co+ CuTaN/Ru + CuMn/Ru+ Cu and/orCo via prefillAlternative metalsVertically integrated DEVICE circuitsNew functional scaling on top of base CMOS:Spintronics, 2D devices , (Steep-Slope switches)Horizontal nanowire stacked devices (CFET)Ch-IIIVCh-GeiNxx = imec node xx; *h/v GAA = horizontal/vertical Gate-All-Around; FinfetFinfetFinfetHGAACONFIDENTIALENHANC E PITCH-BASED SCALING WITH DTCOCONTACTED GATE PITCH SCALING7nm10nm5nm16/14nm9-tracksCGP = 78 SPMP = 64 LELEFP = 48 = 64 SADP/LELEMP = 48 SADP/LELEFP = 36 SAQP3-fin6-tracksCGP = 52 SADPMP = 40 SADP FP = 30 SAQP2-fin6-tracksCGP = 40 SADP MP = 32 EUV SPFP = 24 SAQP2-fin or scalingPitch scalingPitch scalingDTCODTCODTCO1stgen scaling boosters:oM1/CGP gearoSingle diffusion breakoSelf aligned blockoIn line merged viaoOpen M1architecture2ndgen scaling boosters.

3 OSelf aligned gate contactoFully self aligned viaoSuper ViaoBuried power Gate Pitch (CGP) Scaling Gate length scalingFin # scaling Fin height increase or high mobility channelCONFIDENTIAL1520253010Lg (nm)60708090100110120 Subthreshold Swing (mV/dec) DEVICE ARCHITECTURE IMPACTS ELECTROSTATICS FinFETs offered a Low-Voltage transistor option wrt bulk planar. To maintain electrostatics, fin width scaling is necessary. FinW=7-10nmTapered FinLmin~ 28nmStraight FinFinW=7-8nmLmin~ 22-24nmUltra-Thin FinFinW=5nmLmin~ 18nmN22N14N10N7N528-32nmBulk Planar(Vdd~ )FinFETs(Vdd~ )6 CONFIDENTIALFIN SCALING Continuous fin pitch & cd scaling from SADP to SAQP Fin height increase for accelerate scaling and performance High aspect ratio in fin and subsequent modules30 nm45 nm10 nm525 nm50 nm5 nmCONFIDENTIALSCALED FINFET metrology CHALLENGES8 FinFinFin Fin cd Fin height Fin profile Gate cd (@ fin sidewall) Gate height Gate profileCD & overlay measurements in high AR 3D structuresStress measurement in finDopant diffusion & activationin fin & SDDefectsSiGeSi.

4 PComposition in thin film & interfaceCONFIDENTIALIMEC HIGH PERFORMANCE MOBILE LOGIC ROADMAPE arly fdry production2014N14 (industryref.) (V) or HGAAFinFET or HGAAHGAAC hannel nfet/pfetSi / SiSi / Si {SiGe}Si / SiGeSi/ SiGe(Highermobility)Gate Pitch (nm)70-90, 193i64, 193i42,193i32, EUVTBDGate length (nm)30242018-1414-10 Contact metalWWW or CoAlternativemetalAlternative metalMetal Pitch (nm)52-64, 193i42, 193i32, 193i, EUV cut/Via24, EUV18,EUVLow k + CuTaN/Co+ CuTaN/Ru + CuMn/Ru+ Cu and/orCo via prefillAlternative metalsVertically integrated DEVICE circuitsNew functional scaling on top of base CMOS:Spintronics, 2D devices , (Steep-Slope switches)Horizontal nanowire stacked devices (CFET)Ch-IIIVCh-GeiNxx = imec node xx; *h/v GAA = horizontal/vertical Gate-All-Around.

5 FinfetFinfetFinfetHGAACONFIDENTIAL152025 3010Lg (nm)60708090100110120 Subthreshold Swing (mV/dec) DEVICE ARCHITECTURE IMPACTS ELECTROSTATICS FinFETs offered a Low-Voltage transistor option wrt bulk planar. To maintain electrostatics, simple FinFETs will hit limits FinW=7-10nmTapered FinLmin~ 28nmStraight FinFinW=7-8nmLmin~ 22-24nmUltra-Thin FinFinW=5nmLmin~ 18nmNanowire =7nmGate-All-Around NanowireLmin~ 15nmN22N14N10N7N528-32nmBulk Planar(Vdd~ )FinFETs(Vdd~ )10 CONFIDENTIALCMOS LATERAL NANOWIRE DEMONSTRATIONLG= 30 nmPfetNfetNfetPfetHfO2 HfO2 TiAlTiNTaN2 stacked Si lateral nanowires CMOS demonstration with RMGCONFIDENTIAL12 STACKED NANOWIRE FET FLOW Starting material: Si wafer Well implantations SiGe/Si epitaxy SADP fin patterning STI fill Dummy gate patterning Extension implantations Spacer Embedded S/D epitaxy ILD0 (incl.)

6 Poly removal) Dummy oxide removal Sacrificial layer etch HK + WF metal deposition Metal gate fill and CMP LI1 + LI2 + V0 + BEOLSiGe/Si SL epi and STI formationStacked nanowire fabricationby SiGe etch in narrow gate trenches Modifications to the Si FinFET flow(EV-FF):40 Stacked nanowire FET process flow is similar as FinFET. Critical metrologies: FF + nanowire specific metrologiesCONFIDENTIALNANOWIRE SPECIFIC METROLOGIESSi/SiGe multi layer defects and Ge diffusionStacked nanowire diameter and shape & HK/WFM conformalityCONFIDENTIALSCALED HIGH MOBILITY CHANNEL (III-V) GATE-AROUND (GAA) devices ON SILICON Improving III-V GAA Passivation improves performance and scalability 300mm-compatible process developed & record performance for InGaAs achievedRecord InGaAs channel performances for Vdd= ~ 36nm-46nm (NEW)Wfin~ 16nm (NEW)Gmsat> 2000 mS/mmSS ~ 90-100mV/decCONFIDENTIALDEFECT ENGINEERING FOR III-V ON SILICONC.

7 Merckling & IIIV Epi Team Unique defect trapping Innovation allows for InGaAs to be integrated in tight geometry in proximity to Si & other materials Defect characterization is key for high mobility channel integration in FF and HIGH PERFORMANCE MOBILE LOGIC ROADMAPE arly fdry production2014N14 (industryref.) (V) or HGAAFinFET or HGAAHGAAC hannel nfet/pfetSi / SiSi / Si {SiGe}Si / SiGeSi/ SiGe(Highermobility)Gate Pitch (nm)70-90, 193i64, 193i42,193i32, EUVTBDGate length (nm)30242018-1414-10 Contact metalWWW or CoAlternativemetalAlternative metalMetal Pitch (nm)52-64, 193i42, 193i32, 193i, EUV cut/Via24, EUV18,EUVLow k + CuTaN/Co+ CuTaN/Ru + CuMn/Ru+ Cu and/orCo via prefillAlternative metalsVertically integrated DEVICE circuitsNew functional scaling on top of base CMOS:Spintronics, 2D devices , (Steep-Slope switches)Horizontal nanowire stacked devices (CFET)Ch-IIIVCh-GeiNxx = imec node xx; *h/v GAA = horizontal/vertical Gate-All-Around.

8 FinfetFinfetFinfetHGAACONFIDENTIALFinFET GAANo Room forLateralContacted Pitch Vertical Eventually disruptive architectures like Vertical NWs can extend density scaling 201075310406090 Physical Dimension (nm)CMOS Technology Node (nm) Continual gate pitch (density) scaling will be limited by space for Contact & Gate Solution necessary for Lgate scaling and contact area scalingLIMITS TO DENSITY/LGATESCALINGCONFIDENTIAL18 VERTICAL FET PROCESS FLOW Nanowire diameter, shape, & profile control and their metrologies are important in vertical nanowire FET, which is similar as horizontal nanowire. Vertical nanowire FET specific process control & metrology : vertical alignment between gate-SDCONFIDENTIALIMEC HIGH PERFORMANCE MOBILE LOGIC ROADMAPE arly fdry production2014N14 (industryref.)

9 (V) or HGAAFinFET or HGAAHGAAC hannel nfet/pfetSi / SiSi / Si {SiGe}Si / SiGeSi/ SiGe(Highermobility)Gate Pitch (nm)70-90, 193i64, 193i42,193i32, EUVTBDGate length (nm)30242018-1414-10 Contact metalWWW or CoAlternativemetalAlternative metalMetal Pitch (nm)52-64, 193i42, 193i32, 193i, EUV cut/Via24, EUV18,EUVLow k + CuTaN/Co+ CuTaN/Ru + CuMn/Ru+ Cu and/orCo via prefillAlternative metalsVertically integrated DEVICE circuitsNew functional scaling on top of base CMOS:Spintronics, 2D devices , (Steep-Slope switches)Horizontal nanowire stacked devices (CFET)Ch-IIIVCh-GeiNxx = imec node xx; *h/v GAA = horizontal/vertical Gate-All-Around; FinfetFinfetFinfetHGAACONFIDENTIALMOVING TO TUNNEL FET20 LOW VOLTAGE APPLICATIONSCONFIDENTIALTFET INTEGRATION21 PlanarInGaAs TFETV ertical InGaAs TFETV ertical heterojunction TFETVd= (mV/dec)10-610-510-410-310-2Id (uA/um)EOT= nm(c)SS down to 54mV/decby EOT scalingSS down to 75mV/dec Vertical TFET has same challenges as vertical nanowire FET (NW diameter, shape, profile) Heterostructure defect control/metrologyis TFET specific SWING & LEAKAGE DETRACTORS draingatesourcegatepi nAmbipolar Leakage: Low Eg limites VgdDit: Interference & Fermi pinning due to interface defect statesSRH: Thermal Gen.

10 & Recomb. kTECJgSRH2exp1 TAT: Trap-Assisted-TunnelingPhonon-Assisted Tunneling kTEECJT gtrap2exp2 Lateral (Point) Vs. Vertical (Line) Tunneling & resultant DOS FECJgBTBT2/3expTFET performance dominated by heterostructure and defects. metrology of bulk/interface defects in heterostructure is EVALUATION OF DEFECTS23 DLTSN oiseDefect impact evaluated electrically by DTLS and Noise measurement. CONFIDENTIALVan der Waals20 2-D CrystalsLow or free of dangling bondsWide band gapHigh DOS & reasonablemobility for ultra-thin channelsLow-defectivity molecular dopingNatural Nanosheets2-D TRANSITION METAL DICHALCOGENIDES(TMD) CRYSTALS (MX2)VdW heterostructures (No lattice mismatch issues?)