Example: air traffic controller

Computer Architecture Out-of-order Execution

If only one inst. goes into the pipeline each cycle, then on average only one inst. will commit each cycle IPC=1 • Branch prediction Not much parallelism in basic blocks (insts. seq. between branches) Identify ILP across branch (and loop) boundaries • Register renaming Break False- and Anti-dependencies •

Tags:

  Cycle

Information

Domain:

Source:

Link to this page:

Please notify us if you found a problem with this document:

Other abuse

Advertisement

Transcription of Computer Architecture Out-of-order Execution

Related search queries