DATA SHEET - Die Elektronikerseite

1 data SHEETP roduct specificationFile under integrated Circuits, IC04 January 1995 integrated CIRCUITSHEF4027 Bflip-flopsDual JK flip-flopFor a complete data SHEET , please also download: The IC04 LOCMOS HE4000B LogicFamily Specifications HEF, HEC The IC04 LOCMOS HE4000B LogicPackage Outlines/Information HEF, HECJ anuary 19952 Philips SemiconductorsProduct specificationDual JK flip-flopHEF4027 Bflip-flopsDESCRIPTIONThe HEF4027B is a dual JK flip-flop which isedge-triggered and features independent set direct(SD), clear direct (CD), clock (CP) inputs and outputs(O,O). data is accepted when CP is LOW, and transferredto the output on the positive-going edge of the clock.

2 Theactive HIGH asynchronous clear-direct (CD) and set-direct(SD) are independent and override the J, K, and CP outputs are buffered for best system action in the clock input makes the circuithighly tolerant to slower clock rise and fall Functional Pinning TABLESN otes1. H = HIGH state (the more positive voltage)L = LOW state (the less positive voltage)X = state is immaterial= positive-going transitionOn+1= state after clock positive transitionPINNINGFAMILY data , IDD LIMITS category FLIP-FLOPSSee Family SpecificationsINPUTSOUTPUTSSDCDCPJKOOHLX XX HLLHXXX LHHHXXX HHINPUTSOUTPUTSSDCDCPJKOn+1On+1 LLLLno changeLLHL HLLLLH LHLLHHOnOnJ,Ksynchronous inputsCPclock input (L to H edge-triggered)SDasynchronous set-direct input (active HIGH)CDasynchronous clear-direct input (active HIGH)Otrue outputOcomplement outputHEF4027BP(N):16-lead DIL.

3 Plastic (SOT38-1)HEF4027BD(F):16-lead DIL; ceramic (cerdip) (SOT74)HEF4027BT(D):16-lead SO; plastic (SOT109-1)( ): Package Designator North AmericaJanuary 19953 Philips SemiconductorsProduct specificationDual JK flip-flopHEF4027 Bflip-flopsAC CHARACTERISTICSVSS= 0 V; Tamb=25 C; CL= 50 pF; input transition times 20 nsVDDVSYMBOL EXTRAPOLATIONFORMULAP ropagation delaysCP O,O5105210 ns78 ns+(0,55 ns/pF) CLHIGH to LOW10tPHL4080 ns29 ns+(0,23 ns/pF) CL153060 ns22 ns+(0,16 ns/pF) CL585170 ns58 ns+(0,55 ns/pF) CLLOW to HIGH10tPLH3570 ns27 ns+(0,23 ns/pF) CL153060 ns22 ns+(0,16 ns/pF) CLSD O570140 ns43 ns+(0,55 ns/pF) CLLOW to HIGH10tPLH3060 ns19 ns+(0,23 ns/pF) CL152550 ns17 ns+(0,16 ns/pF) CLCD O5120240 ns93 ns+(0,55 ns/pF) CLHIGH to LOW10tPHL4590 ns33 ns+(0,23 ns/pF) CL153570 ns27 ns+(0,16 ns/pF) CLSD O5140280 ns113 ns+(0,55 ns/pF)

4 CLHIGH to LOW10tPHL55110 ns44 ns+(0,23 ns/pF) CL154080 ns32 ns+(0,16 ns/pF) Logic diagram (one flip-flop).January 19954 Philips SemiconductorsProduct specificationDual JK flip-flopHEF4027 Bflip-flopsCD O575150 ns48 ns+(0,55 ns/pF) CLLOW to HIGH10tPLH3570 ns24 ns+(0,23 ns/pF) CL152550 ns17 ns+(0,16 ns/pF) CLOutput transition times560120 ns10 ns+(1,0 ns/pF) CLHIGH to LOW10tTHL3060 ns9 ns+(0,42 ns/pF) CL152040 ns6 ns+(0,28 ns/pF) CL560120 ns10 ns+(1,0 ns/pF) CLLOW to HIGH10tTLH3060 ns9 ns+(0,42 ns/pF) CL152040 ns6 ns+(0,28 ns/pF) CLSet-up time55025nssee also waveformsFigs 4 and 5J,K CP10tsu3010ns15205nsHold time5250nsJ,K CP10thold200ns15155nsMinimum clock58040nspulse width.

5 LOW10tWCPL3015ns152412nsMinimum SD,CD5tWSDH,tWCDH9045nspulse width; HIGH104020ns153015nsRecovery time5tRSD,tRCD20 15nsfor SD,CD1015 10ns1510 5nsMaximum clock548 MHzsee also frequency10fmax1225 MHzJ = K = HIGH151530 MHzVDDVTYPICAL FORMULA FOR P ( W)Dynamic power5900 fi+ (foCL) VDD2wheredissipation per104 500 fi+ (foCL) VDD2fi= input freq. (MHz)package (P)1513 200 fi+ (foCL) VDD2fo= output freq. (MHz)CL= load capacitance (pF) (foCL) = sum of outputsVDD= supply voltage (V)VDDVSYMBOL EXTRAPOLATIONFORMULAJ anuary 19955 Philips SemiconductorsProduct specificationDual JK flip-flopHEF4027 Bflip-flopsAPPLICATION INFORMATIONSome examples of applications for the HEF4027B are: Registers Counters Control showing set-up times, hold times and minimum clock pulse width.

6 Set-up and hold times areshown as positive values but may be specified as negative Waveforms showing recovery times for SDand CD; minimum SDand CDpulse widths.