DEPARTMENT OF ELECTRONICS & …

1 APPROVED BY AICTE NEW DELHI, AFFILIATED TO VTU BELGAUM DEPARTMENT OF ELECTRONICS & communication engineering digital ELECTRONICS laboratory LAB manual 15 ECL38 III-SEMESTER 2016-2017 Prepared by: Reviewed by: Approved by: Mrs. A. Deepa Mrs. Kavitha M V Dr. Powly Thomas Assistant Professor Head of the DEPARTMENT Principal Dept. of ECE Dept. of ECE GCEM GCEM GCEM 81/1, 182/1, Hoodi Village, Sonnenahalli, Puram, Bengaluru, Karnataka-560048.

2 1 Contents Title Page No 1. Syllabus 2-2 2. Course objective 2-2 3. Course outcome 3-3 4. Do s & Don ts 4-4 5. List of experiments 5-46 6. Viva questions 47-48 7. Appendix-1 49-52 2 Syllabus digital ELECTRONICS laboratory [As per Choice Based Credit System (CBCS) scheme] SEMESTER III (EC/TC) laboratory Code 15 ECL38 IA Marks 20 Number of Lecture 01Hr Tutorial (Instructions) Exam Marks 50 Hours/Week + 02 Hours laboratory laboratory Experiments: 1.

3 Verify (a) Demorgan s Theorem for 2 variables. (b) The sum-of product and product-of-sum expressions using universal gates. 2. Design and implement (a) Full Adder using basic logic gates. (b) Full subtractor using basic logic gates. 3. Design and implement 4-bit Parallel Adder/ subtractor using IC 7483. 4. Design and Implementation of 4-bit Magnitude Comparator using IC 7485. 5. Realize (a) 4:1 Multiplexer using gates. (b) 3-variable function using IC 74151(8:1 MUX). 6. Realize 1:8 Demux and 3:8 Decoder using IC74138. 7. Realize the following flip-flops using NAND Gates.

4 (a) Clocked SR Flip-Flop (b) JK Flip-Flop. 8. Realize the following shift registers using IC7474 (a) SISO (b) SIPO (c) PISO (d)PIPO. 9. Realize the Ring Counter and Johnson Counter using IC7476. 10. Realize the Mod-N Counter using IC7490. 11. Simulate Full- Adder using simulation tool. 12. Simulate Mod-8 Synchronous UP/DOWN Counter using Simulation tool. 3 Course Objectives: This laboratory course enables students to get practical experience in design, realization and verification of Demorgan s Theorem, SOP, POS forms Full/Parallel Adders, Subtractors and Magnitude Comparator Multiplexer using logic gates Demultiplexers and Decoders Flip-Flops, Shift registers and Counters.

5 Course Outcomes: On the completion of this laboratory course, the students will be able to: Demonstrate the truth table of various expressions and combinational circuits using logic gates. Design, test and evaluate various combinational circuits such as adders, subtractors, comparators, multiplexers and demultiplexers. Construct flips-flops, counters and shift registers. Simulate full adder and up/down counters. 4 Do s & Dont s Do s Conduct yourself in a responsible manner at all times in the laboratory . Dress properly during a laboratory activity.

6 Long hair, dangling jewelry and loose or baggy clothing are a hazard in the laboratory . Observe good housekeeping practices. Replace the materials in proper place after work to keep the lab area tidy. Dont s Do not wander around the room, distract other students, startle other students or interfere with the laboratory experiments of others. Do not eat food, drink beverages or chew gum in the laboratory and do not use laboratory glassware as containers for food or beverages. Do not open any irrelevant internet sites on lab computer Do not use a flash drive on lab computers.

7 Do not upload, delete or alter any software on the lab PC. Do not switch on the trainer kit without verifying connection. 5 List of Experiments EXPT. NO. Name of the Experiment PAGE NO. Introduction Study of Logic gates 7 01 To verify (a) Demorgan s Theorem for 2 variables (b) The sum-of product and product-of-sum expressions using universal gates 10 02 To design and implement (a) Full Adder using basic logic gates. (b) Full subtractor using basic logic gates. 14 03 To design and implement 4-bit Parallel Adder/ subtractor using IC 7483.

8 18 04 Design and Implementation of 4-bit Magnitude Comparator using IC 7485. 21 05 To realize (a) 4:1 Multiplexer using gates (b) 3-variable function using IC 74151(8:1 MUX) 23 06 Realize 1:8 Demux and 3:8 Decoder using IC74138. 27 07 To realise the following flip-flops using NAND Gates. (a) Clocked SR Flip-Flop (b) JK Flip-Flop 29 08 To realize the following shift registers using IC7474 (a) SISO (b) SIPO (c)PISO 32 09 To realize the Ring Counter and Johnson Counter using IC7476. 39 10 To realize the Mod-N Counter using IC7490. 42 11 Simulate Full- Adder using simulation tool.

9 44 12 Simulate Mod-8 Synchronous UP/DOWN Counter using simulation tool. 46 6 INTRODUCTION STUDY OF LOGIC GATES Aim: Truth Table verification of logic gates General Characteristics: a. Pin Vcc on an is to be connected to a regulated power supply of +5 volts. b. Pin GND on an is to be connected to the power supply ground. c. = High or 1 state implies a voltage between and in the input state. Procedure: 1. Fix the on the trainer kit. 2. Connections are made as shown, using the pin details of the gates. Toggle switches and LED s in the trainer are used as inputs and outputs respectively.

10 3. Switch on the supply on the trainer and verify the truth table of the gates AND GATE (7408) Truth Table A B Y= 0 0 0 0 1 0 1 0 0 1 1 1 YBA43567408 GND789101411121321 VCC7 OR GATE (7432) Truth Table A B Y=A+B 0 0 0 0 1 1 1 0 1 1 1 1 NOT GATE (7404) Truth Table A Y= 0 1 1 0 YAB912341410811137126 VCC5 GND74328 NAND GATE (7400) Truth Table A B 0 0 1 0 1 1 1 0 1 1 1 0 NOR GATE (7402) Truth Table A B 0 0 1 0 1 0 1 0 0 1 1 0 ABYYBA43567402 GND789101411121321 VCC9 EX-OR GATE (7486) Truth Table A B Y=A B 0 0 0 0 1 1 1 0 1 1 1 0 ABY43567486 GND789101411121321 VCC 10 Experiment No: 01 Date: AIM: 1.