Design and Assembly Process Implementation for …

1 IPC-7094 Design and AssemblyProcess Implementationfor flip Chip and DieSize ComponentsDeveloped by the flip Chip Mounting Strategy Task Group of theAssembly & Joining Processes Committee of IPCU sers of this publication are encouraged to participate in thedevelopment of future :IPC3000 Lakeside Drive, Suite 309 SBannockburn, Illinois60015-1249 Tel 847 847 Table of .. 12 APPLICABLE .. 23 REQUIREMENTS AND and definitions .. or Die .. Element .. Package .. Module .. of flip Chip Mounting .. of flip Chip Mounting .. of Die Size and Chip Scale ArrayPackaging .. BGA ( BGA) .. BGA .. Outline No Lead Chip Scale Packages(SON and QFN) .. of Die Size Package Technology .. 74 flip CHIP Design Consideration .. Circuitry .. Metal Traces .. and capacitance .. Frequency Performance .. Design .. Interconnect Thermal Model.

2 Chip Preparation for Mounting .. Guide Checklist .. Metal .. Passivation .. Population .. Output Requirements .. Metal Reticle Mask .. (Terminal Via) Reticle Maskand Plan .. Cell Design .. Board Land Pattern Design .. Pattern for Ceramic Substrate Design .. Bumping .. Paste Deposition .. Electroplating .. Bumping Techniques and Materials .. and Bump Contact Process forFlip Chip .. Control .. Integrity .. of Bumping Site .. Redistribution .. 175 flip CHIP POST FAB and Reliability Screening .. Good Die (KGD) .. Quality Die (KQD) .. Testing and Equipment Challenges/Concerns .. Screening at the Wafer orDie Level .. Thinning (Grinding and Polishing) .. and Polishing Process .. Effect on the Quality of the Die .. (Sawing) .. Sawing .. and Handling .. 206 flip CHIP INTERCONNECTING Base Material.

3 Base Substrates .. Resin Substrates .. Conductor Base Metals for Flexibleand Reinforced Laminates .. Substrates .. Based Substrates .. Finish Properties .. Plating Finishes (Electrolyticand Electroless) .. Film Metallic Finishes .. Film Deposition Processes .. (Thin Film) Conductive Finishes .. Metal Deposition Process .. 247 PACKAGE LEVEL Physical Features .. for flip Chip and Die Size(DSBGA) Packaging .. 25 February Chip Development and PerformanceStandards .. Chip IC Component Design .. Fabrication and Bond Site Planning .. Level Contact FormingMethodologies .. Standards for Wafer Level BallGrid Array .. Pad and Array Planning .. Factor: Bump Attachment andBonding .. Integrity .. Array Redistribution .. Shrink Considerations .. Outline Standards for Die-SizeBall Grid Array (DSBGA) Packaging.

4 Standard for Die Size BGA .. Contact Measurement .. Outline Consideration .. Performance Planning .. and Simulation .. Radiation .. Bias Created by NonelectricalPhenomena .. for Package Level SubstrateDesign and Performance .. and Performance of OrganicStructures for flip Chip Mounting .. and Performance for OrganicSingle and Multichip Mounting andInterconnecting Structures .. and Performance Standardfor Inorganic Mounting Structures .. Methods for Qualification andEvaluation of flip Chip MountingStructures .. Performance Test Requirements .. Chip and Chip-Scale Package Assembly .. Material Requirements .. for Bump and Ball ContactAlloy .. for flip Chip and Chip-Size PackageMounting .. Paste for flip Chip and Chip-SizePackage Mounting .. Conductive Adhesives for FlipChip Attachment .. Material Requirements.

5 Material Requirements .. Chip and Chip-Scale AssemblyPerformance Requirements .. Cycle Stress Testing of SolderedAssemblies .. for flip Chip and Chip-Size Packages(Shipping and Delivery) .. 358 SYSTEM-LEVEL for Assembly .. Chip, DSBGA Land Pattern Design .. Clearance .. Organic Substrate Design .. Compliant Surface Finish Selection .. Circuit Substrate Design .. for Harsh Environments .. Substrates .. Substrate Design .. Film on Ceramic Substrates .. Film on Ceramic Substrates .. Layer Ceramic Substrates .. Design Guide Checklist: .. 419 flip CHIP/DIE SIZE DEVICE Preparation .. Chip and Die-Size Device Placement .. Processes .. Attachment Process for flip Chip .. Soldering .. Alloys and Process Parameters .. Stencil Development .. Process Profile Planning .. Process Implementation .

6 Process Evaluation .. and Ultrasonic Bonding .. Interconnection .. Conductive Adhesives .. Conductive Adhesives .. Adhesive Process .. flip Chip Processes .. flip Chip Cleaning Technology .. Assessment .. Inspection .. Inspection .. ( flip Chip Encapsulation) .. Flow Underfill Process Overview .. (No Flow) Underfill .. Underfill .. 49 IPC-7094 February Surface Compatibility .. Test .. Hot Air Device Removal Process .. Laser Process for Device Removal .. 5110 REQUIREMENTS FOR BOARD/MODULELEVEL of Products to Use .. Scale Package Robustness andReliability .. Factors .. Wear-Out Mechanisms .. Creep-Fatigue Interaction .. Electro-Migration .. Corrosion .. Thermo-Migration .. Bump Mechanical Reliability .. Strain .. Effect of Thermal Expansion Mismatch.

7 Temperature Cycling Frequency .. Mechanisms Review .. Reliability Factors .. Benefits of Reinforcement .. Related Failures .. for Reliability (DfR) .. Mechanisms and Failure ofSolder Attachments .. Solder Joints and Attachment Types .. Solder Interface Grain Structure Effects .. Global Expansion Mismatch .. Local Expansion Mismatch .. Internal Expansion Mismatch .. Solder Attachment Failure .. 5711 RELIABILITY PREDICTION Temperature Excursions .. Modeling .. Failure Distribution and FailureProbability .. Modeling .. 5812 VALIDATION AND QUALIFICATION Procedures .. Solder Joints .. Scenarios .. Environmental Testing .. Testing for KGD .. and Process Control Assurance .. Quality Management andManufacturing (TQMM) .. 6013 SUPPLY CHAIN Management .. 6014 FUTURE Factor.

8 Challenges for IC Packagesand Electronic Modules .. Infrastructure .. Materials .. Equipment .. Circuit Imaging .. 61 APPENDIX 62 APPENDIX 67 FiguresFigure 3-1 Solid Copper Core Ball Contact .. 3 Figure 3-2 flip Chip with a Silver Coated CopperCore Bump to Maintain a Uniform Stand-Off Height .. 3 Figure 3-3 The uncased WLBGA, when preparedwith compatible alloy bump contacts, canbe reflow soldered directly onto the nextlevel Assembly .. 4 Figure 3-4 The mm x mm die size packageabove has 46 I/O, mm pitch and 350micron ball diameter.. 4 Figure 3-5 flip Chip Mounted onto a FBGA SubstrateInterposer .. 5 Figure 3-6 The die face-up CSP with wire-bond die-to-substrate interface is typically only twentypercent larger than the die outline.. 5 Figure 3-7 The Flex-Based Lead-Bond BGA isa Die-Size Package .. 5 Figure 3-8 The combination of package materials andthe S bend lead of the BGA compensatesfor the expansion mismatch between thedie and circuit board interface.

9 6 Figure 3-9 The Mini BGA provides a ball pitch thatis more compatible with conventionalSMT Assembly processing.. 6 Figure 3-10 The SLICC package is a bumped flipchip mounted onto an organic substratestructure.. 6 Figure 3-11 Wire-Bond Pad to Array RedistributionProvides Wider Spacing and LargerContact Features .. 6 Figure 3-12 The SON and QFN are ideal low cost CSPfor relatively low I/O device packaging .. 7 Figure 4 1 Bump Equivalent Circuit (Redistributed Chip) .. 8 Figure 4-2 Bump Electrical Path (Redistributed Chip) .. 8 Figure 4-3 Final Metal Trace and Underlying Traces(Cross-Section) .. 9 February 2009 IPC-7094viiFigure 4-4 Thermal/Electrical Analogy .. 9 Figure 4-5 Bump Interconnect Equivalent Model .. 9 Figure 4-6 Alignment to Visual/Sensitive ChipStructures .. 11 Figure 4-7 Minimum Pitch from Bump to PassivationSeal .. 11 Figure 4 8 Two Simple Chips, Showing Original PadLocations and Rerouted Bumps.

10 12 Figure 4 9 Redistribution of a Single Metal LayerDevice .. 12 Figure 4 10 Passivation (Cross-Section) .. 12 Figure 4 11 Suggested Distribution of RedundantBump Contacts .. 13 Figure 4 12 Array Design Anticipating the Potentialfor Die Shrink .. 13 Figure 4 13 Signal and Power Distribution Position .. 14 Figure 4 14 Nested I/O Contacts .. 14 Figure 4 15 Typical Bump Passivation Reticle MaskFormat for Peripheral and Array ContactVariations .. 14 Figure 4 16 Product Unit Cell Plan (Example) .. 15 Figure 4 17 Printed Board flip Chip or Array LandPatterns .. 15 Figure 4 18 Land Pattern Planning for flip ChipAttachment to a Ceramic BasedSubstrate .. 15 Figure 4 19 Mass Reflow Solder Bumping of theDie While in a Wafer Format .. 15 Figure 4 20 Gold Stud-Bump Contact ProfileComparing a Wire Break-Off to aMore Uniform Cut Wire Profile.