DESIGNWARE DW8051 MACROCELL SOLUTION

1 OVERVIEWThe DESIGNWARE DW8051 MACROCELL is a high-performance, configurable, fully-synthesizable, and reusable8051 core. It is fully binary compatible with the industry standard 803x/805x microcontrollers. An encrypted version of the DW8051 MACROCELL is available to all DESIGNWARE Foundation Library usersat no cost. Unencrypted VHDL and Verilog source code versions are also available. Both the encrypted andsource code versions include Synopsys coreConsultant for automatic installation, configuration, simulation, andsynthesis of the DW8051 . HIGHPERFORMANCE ANDPORTABILITYThe DESIGNWARE DW8051 MACROCELL SOLUTION includes the DW8051 MACROCELL , a referencedesign, and our extensive verification environment. The DW8051 s high-performance architectureprovides up to three times the performance improvement over the standard 8051 whenoperating at the same clock DW8051 synthesizes automatically through coreConsultant to run at greater than 120 MHz in processes.

2 The DW8051 is technology independent and can be implemented in a variety of DW8051 has been fabricated in both ASIC and FPGA , COMPLETESOLUTIONTo ensure quality, the DW8051 was developed according to Synopsys strict design-for-reusemethodology. The DW8051 has undergone extensive testing during the design process and hasbeen proven in many different technologies. The DW8051 has also been tested with a varietyof third-party 8051 development tools and 8051 evaluation DW8051 s high-performance, configurable, synthesizable architecture, along with thedevelopment environment provided and supported by Synopsys, provide a total SOLUTION forbuilding low-cost, high-performance embedded control systems for a wide range of MACROCELLSOLUTIONThe synthesizable DesignWareDW8051 MACROCELL provides up to three times the performanceof standard 8051 microcontrollerswhile operating at the same clock Y N O P S Y S sfr_data_inmem_data_inmem_ea_niram_data_ outirom_data_outint0_nint1_nint2int3_nin t4int5_npfiwdtit0t1t2t2exrxd0_inrxd1_int est_mode_nrst_in_npor_nclksfr_addrsfr_da ta_outsfr_wrstr_rdmem_addrmem_data_outme m_wr_nmem_rd_nmem_pswr_nmem_psrd_nmem_al eiram_addriram_data_iniram_rd_niram_we1_ iniram_we2_nirom_addrirom_rd_nirom_cs_np ort_pin_reg_np0_mem_reg_np0_addr_data_np 2_mem_reg_ntxd0rxd0_outtxd1rxd1_outt0_ou tt1_outt2_outstop_mode_nidle_mode_nrst_o ut_nDW8051 INPUT/OUTPUTSIGNALSDW8051

3 Rev. 5/99 7/7/99 3:38 AM Page 1 AUTOMATEDDESIGNFLOW WITHSYNOPSYSCORECONSULTANTThe current version of the DW8051 MacroCellsolution has been developed and packaged for usewith Synopsys coreConsultant. coreConsultant, inturn, provides the following services:nAutomatic installation of the DW8051 coreKit nActivity checklist that guides you through DW8051 design activities in the correct ordernAutomatic, error-free DW8051 configuration, including parameter cross-dependency checkingnAutomatic configuration and operation of the DW8051 verification environment nAutomatic, high-quality synthesis with your technology library and your installed version ofDesign Compiler nAutomatic design checking and synthesis results analysis You can operate coreConsultant either in its GUImode (Figure 1) or in batch mode through itscommand line E S I G N W A FIGURE1: EXAMPLE CORECONSULTANTDIALOGS FORDW8051DW8051 rev.

4 5/99 7/7/99 3:38 AM Page 2 TECHNICALADVANTAGES OF THEDW8051n 4 clocks/instruction cycle versus 12 in standard 8051 Up to three times faster execution on averageversus standard 8051n Stretch memory cycle Allows application software to adjust todifferent external RAM speeds MOVX in as little as eight clock cyclesn Dual data pointers Improves efficiency when moving largeblocks of datan Internal/external peripheral interface Special function register (SFR) bus in DW8051supports both internal and external peripherals vs. internal only in standard 8051n Two optional full-duplex serial portsn Seven additional interruptsn SFR bus for adding custom peripherialsDW8051 FEATURESThe DW8051 MACROCELL is reusable in designenvironments that include widely used EDA tools forsimulation ( , VCS , VHDL System Simulator (VSS), MTI ModelSim, Leapfrog, and Verilog-XL),Synopsys Design Compiler for synthesis, andSynopsys Test Compiler for CompatibilityThe DW8051 is compatible with the standard 8051 instruction set and can be configured to a widerange of industry standard 803x/805x architectures.

5 Control signals for standard 803x/805x I/O ports are included. Optional full-duplex serial ports and third timer are selectable through ArchitectureDW8051 s design is fully static and efficiency and performance are achieved byeliminating wasted bus cycles, and by providingdual data pointers for moving large data DW8051 core is typically 10k-13k gatesdepending on configuration and the technology itis implemented in. It runs from 0 megahertz togreater than 120 megahertz. (Clock rates greaterthan 100 megahertz require a target technology micron or less). Lower performance applicationsalso benefit by being able to run at lower clockrates to get the same performance as a standard12 clocks/instruction8051. Lower clock rates leadto lower power consumption and lower electro-mag-netic interference (EMI).

6 Adding Custom Designed PeripheralsA typical 8051 allows peripheral interface onlythrough port logic. In addition to the ports, theDW8051 also provides direct access to peripheralsthrough the memory and SFR buses (Figure 2):n You can interface additional peripherals directlyto the DW8051 s memory bus. This method allows you to make use of the stretch memory cycle feature to interface slow You can also directly attach custom designed peripherals to the efficient SFR bus, the same bus used for interfacing standard DW8051 internal peripherals. SFR addresses that are not used for DW8051 internal SFRs are available forconnecting external peripherals. Adding peripherals to the SFR bus offers the following advantages: R E D W 8 0 5 1DW8051 rev.

7 5/99 7/7/99 3:38 AM Page 3 Faster read, write accesses; 1 clock vs. 2 clocks using mem_bus Direct addressing Can take advantage of bit manipulation instructions Efficient, compact code Third-Party Development Tools SupportSynopsys has an active program in place to supportthird-party tools. Many industry standard compilers,assemblers, ROM monitors, and in-circuit emulatorshave been tested for compatibility with the allows integration of these tools into a designenvironment and provides a complete developmentsolution for DW8051 -based embedded systems ona chip. In-circuit emulation support is provided byNohau Corporation and Hitex Development CONFIGURABLEARCHITECTUREF igure 3 illustrates the hardware architecture of theDW8051 core.

8 The name of the top-level module is DW8051_core. The internal RAM and ROMmodules are located outside DW8051_core tofacilitate simulation and insertion of technology-specific RAM/ROM modules. The followingsubmodules andinterfaces are selectable throughparameter settings:n DW8051_core can address either 128 or 256 bytes of internal RAMn The internal ROM address range is determined by a parameter (rom_addr_size)n Timer 2 (DW8051_timer2) is optionaln 0,1, or 2 serial ports (DW8051_serial) can be implementedn The interrupt unit is either DW8051_intr_0(6-source) or DW8051_intr_1 (13-source) coreConsultant automatically generates your selectedDW8051 configuration so that no HDL source codeediting is E S I G N W A DW8051_cpuDW8051_coreport_controlmem_bus interruptsclkpor_nrst_in_nrst_out_ntest_ mode_nidle_mode_nstop_mode_ntxd1rxd1_inr xd1_outtxd_0rxd0_inrxd0_outsfr_bust0,t1t 0_out,t1_outt2t2ext2_outiram_busirom_bus Internal ROM(0 to 64 KB)

9 DW8051_intr_0orDW8051_intr_1 Interrupt UnitDW8051_controlDW8051_aluDW8051_biuDW 8051_op_decoderInternal RAM(128 or 256 bytes)DW8051_main_regsDW8051_timerTimer 0 and 1DW8051_serialSerial Port 0(optional)DW8051_timer2 Timer2(optional)DW8051_serialSerial Port 1(optional)FIGURE3: DW8051_COREFIGURE2: DW8051 EXTERNALSFR ANDMEMORYBUSESDW8051 rev. 5/99 7/7/99 3:38 AM Page 4 R E D W 8 0 5 1803X/805 XFEATURECOMPARISONT hrough parameter settings, you can configure theDW8051 hardware to be functionally compatiblewith a variety of 803x/805x configurations. Forexample, you can implement two 16-bit timers for compatibility with the Intel 8051, or you canimplement three for compatibility with the Intel80C32. Table 1 provides a feature-by-feature comparison of the DW8051 MACROCELL and severalcommon 803x/805x DW8051 processor core offers increased performance by executing instructions in a 4-clock buscycle, as opposed to the 12-clock bus cycle in thestandard 8051 (Figure 4).

10 The shortened bus tim-ing improves the instruction execution rate for mostinstructions by a factor of three over the standard8051 architectures. Some instructions require a different number ofinstruction cycles on the DW8051 than they do on the standard 8051. In the standard 8051, allFIGURE4: INSTRUCTIONCYCLETIMINGCOMPARISONF eatureIntelDallasDS80C320 DesignWareDW80518031805180C3280C52 Clocks Per Instruction CycleInternal ROM (1)Internal RAM (1)Data PointersSerial Ports16-bit TimersInterrupt Sources (total of int. and ext.)Stretch Memory Cycle12 128 bytes1125No124KB128 bytes1125No12 256 bytes1136No128KB256 bytes1136No4 256 bytes22313 Yes4Up to 64KB128 bytes or 256 bytes20,1, or 22 or 36 or 13 Yes(1) Internal ROM and RAM are located outside of : FEATURESUMMARY OFDW8051 ANDCOMMON803X/805 XCONFIGURATIONSALEXTAL1AD0-AD7 ALEPORT2 Timing of 8051 Built With DW8051_coreStandard 8051 TimingPORT2AD0-AD74 cycles12 cyclessingle byte singlecycle instructionPSENPSEN single byte singlecycle instructionDW8051 rev.