Device Operation & Timing Diagram - Samsung us

1 Rev. , DDR4 SDRAM Specification CAUTION : The 3DS contents in this document includes some items still under discussion in JEDEC. Therefore, those may be changed without pre-notice based on JEDEC progress In addition, it is highly recommended that you not send specs without Samsung 's permission Device Operation & Timing Diagram Samsung ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND. SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise.

2 Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. 2014 Samsung Electronics Co., Ltd. All rights reserved. -1- Rev. Device Operation DDR4 SDRAM. Revision History Revision No. History Draft Date Remark Editor - First Spec release Sep. 2014 - - Add 3DS Functional Description,3DS SDRAM Command Description Oct. 2014 - and Operation -2- Rev. Device Operation DDR4 SDRAM. Table Of Contents DDR4 SDRAM Specification 1.

3 Functional Description .. 6. Simplified State Diagram .. 6. Basic 7. RESET and Initialization Procedure .. 8. Power-up Initialization 8. VDD Slew rate at Power-up Initialization Sequence .. 9. Reset Initialization with Stable Power .. 9. Register Definition .. 11. Programming the mode registers .. 11. Mode Register .. 13. 3DS Functional Description .. 24. Simplified State 24. Basic Functionality .. 24. Reset Signal and Initialization Procedure .. 24. Mode Register 24. 2. DDR4 SDRAM Command Description and Operation .. 29. Command Truth 29. CKE Truth 30. Burst Length, Type and Order .. 31. BL8 Burst order with CRC 31. DLL-off Mode & DLL on/off Switching procedure .. 32. DLL on/off switching 32. DLL on to DLL off 32. DLL off to DLL on 33. DLL-off 35. Input Clock Frequency Change .. 36. Write 37. DRAM setting for write leveling & DRAM termination function in that mode.

4 37. Procedure 38. Write Leveling Mode Exit .. 40. Temperature controlled Refresh modes .. 40. Normal temperature mode ( 0 C =< TCASE =< 85 C ) .. 40. Extended temperature mode ( 0 C =< TCASE =< 95 C ).. 40. Fine Granularity Refresh Mode .. 41. Mode Register and Command Truth Table .. 41. tREFI and tRFC parameters .. 41. Changing Refresh 42. Usage with Temperature Controlled Refresh mode .. 42. Self Refresh entry and exit .. 43. Multi Purpose Register .. 43. DQ Training with MPR .. 43. MR3 definition .. 43. MPR 44. MPR Writes .. 46. MPR Read Data 49. Data Mask(DM), Data Bus Inversion (DBI) and 55. ZQ Calibration Commands .. 57. ZQ Calibration Description .. 57. DQ Vref 59. Example scripts for VREFDQ Calibration Mode: .. 61. Per DRAM Addressability .. 64. CAL Mode (CS_n to Command Address Latency) .. 66. CAL Mode Description .. 66. Self Refresh Entry, Exit Timing with 69.

5 Power Down Entry, Exit Timing with CAL .. 69. 70. CRC Polynomial and logic 70. CRC data bit mapping for x8 71. CRC data bit mapping for x4 71. -3- Rev. Device Operation DDR4 SDRAM. CRC data bit mapping for x16 71. Write CRC for x4, x8 and x16 devices .. 72. CRC Error Handling .. 72. CRC Frame format with BC4 .. 73. Simultaneous DM and CRC Functionality .. 76. Simultaneous MPR Write, Per DRAM Addressability and CRC Functionality .. 76. Command Address Parity( CA Parity ) .. 77. CA Parity Error Log Readout .. 82. Control Gear-down Mode .. 82. DDR4 Key Core Timing .. 85. Programmable 88. Write Preamble .. 88. Read Preamble .. 89. Read Preamble Training .. 90. 91. Read 91. Write 91. ACTIVATE Command .. 92. Precharge Command .. 92. Read Operation .. 92. READ Timing 92. READ Timing ; Clock to Data Strobe relationship .. 94. READ Timing ; Data Strobe to Data 95.

6 TLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation .. 97. tRPRE Calculation .. 99. tRPST Calculation .. 100. READ Burst Operation .. 101. Burst Read Operation followed by a 112. Burst Read Operation with Read DBI (Data Bus Inversion).. 114. Burst Read Operation with Command/Address Parity .. 115. Read to Write with Write 116. Read to Read with CS to CA Latency .. 117. Write Operation .. 118. Write Timing Parameters .. 118. Write Data 119. tWPRE 120. tWPST Calculation .. 121. Write Burst 122. Read and Write Command 138. Write Timing Violations .. 138. Motivation .. 138. Data Setup and Hold Offset Violations .. 138. Strobe and Strobe to Clock Timing Violations .. 138. Refresh Command .. 139. Self refresh Operation .. 141. Low Power Auto Self Refresh .. 142. Self Refresh Exit with No Operation 143. Power down 144. Power-Down Entry and Exit .. 144. Power-Down 149.

7 Power Down Entry and Exit Timing during Command/Address Parity Mode is Enable .. 150. Maximum Power Saving 151. Maximum power saving mode .. 151. Mode entry .. 151. CKE transition during the mode .. 152. Mode 152. Timing parameter bin of Maximum Power Saving Mode for DDR4-1600/1866/2133/2400/2666/3200 .. 153. Connectivity Test Mode .. 154. Introduction .. 154. Pin Mapping .. 154. Logic 155. Min Term 155. Output equations for x16 devices .. 155. -4- Rev. Device Operation DDR4 SDRAM. Output equations for x8 devices .. 155. Output equations for x4 devices .. 155. Input level and Timing Requirement .. 156. Connectivity Test ( CT ) Mode Input Levels .. 157. Input Levels for RESET_n .. 158. Input Levels for 158. CLK to Read DQS Timing parameters .. 159. Post Package Repair (PPR) .. 161. DDR4 Post Package Repair Guard Key .. 161. Post Package Repair of a Fail Row 161.

8 Fail Row Address Repair (WRA case) .. 162. Fail Row Address Repair (WR case) .. 162. Programming PPR support in MPR0 page2 .. 164. Required Timing Parameters .. 164. Soft Post Package Repair (sPPR) .. 165. Soft Repair of a Fail Row Address .. 165. TRR Mode - Target Row Refresh .. 166. TRR Mode Operation .. 167. MR2 Register Definition .. 168. 3DS SDRAM Command Description and Operation .. 169. ACTIVATE Command .. 169. Precharge and Precharge All 170. Read and Write 171. Refresh Command .. 173. Self-Refresh Operation and Power-Down Modes .. 174. Write Leveling .. 174. ZQ Calibration 174. Command Address Parity (CA Parity).. 175. Target Row Refresh (TRR) .. 176. Post Package Repair (PPR).. 176. 3. On-Die 177. ODT Mode Register and ODT State 178. Synchronous ODT Mode .. 180. ODT Latency and Posted ODT .. 180. Timing Parameters .. 180. ODT during Reads.

9 182. Dynamic ODT .. 183. Functional 183. ODT Timing Diagrams .. 184. Asynchronous ODT mode .. 185. ODT buffer disabled mode for Power down .. 186. ODT Timing Definitions .. 187. Test Load for ODT Timings .. 187. ODT Timing Definitions .. 187. -5- Rev. Device Operation DDR4 SDRAM. 1. Functional Description Simplified State Diagram from any RESET MPSM. MPSM IVREFDQ, state RTT,Etc MRS. MRS SRX w/ SRX w/NOP. NOP CKE_L. Power MRS. w/ Q=Low MRS,MPR, Applied Power Reset On Procedure Initialization PDA Write Leveling Self mode VrefDQ training Refreshing MRS. w/ DQ0=Low SRE. ZQCL SRX. TEN. ZQCS,ZQCL REF. ZQ. Calibration Idle Refreshing RESET. PDE. Connectivity PDX. Test ACT Precharge Power Down CKE_L Activating CKE_L. Active Power Down PDX. PDE. Bank Active Read Write Write Read WriteA ReadA. Writing Read Reading Write WriteA ReadA. WriteA ReadA. PRE, PREA. Writing Reading PRE, PREA PRE, PREA.

10 Precharging Automatic Sequence Command Sequence Abbreviation Function Abbreviation Function Abbreviation Function ACT Activate Read RD,RDS4, RDS8 PDE Enter Power-down PRE Precharge Read A RDA, RDAS4, RDAS8 PDX Exit Power-down PREA PRECHARGE All Write WR, WRS4, WRS8 with/without CRC SRE Self-Refresh entry MRS Mode Register Set Write A WRA,WRAS4, WRAS8 with/without CRC SRX Self-Refresh exit Refresh, Fine granular- REF RESET_n Start RESET procedure MPR Multi Purpose Register ity Refresh Boundary Scan Mode TEN. Enable NOTE : 1. This simplified State Diagram is intended to provide an overview of the possible state transitions and the commands to control them. In particular, situations involving more than on bank, the enabling or disabling of on-die termination, and some other events are not captured in full detail. -6- Rev. Device Operation DDR4 SDRAM. Basic Functionality The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as sixteen-banks, 4 bank group with 4 banks for each bank group for x4/x8 and eight-banks, 2 bank group with 4 banks for each bankgroup for x16 DRAM.