Differential Amplifier Stages - MIT OpenCourseWare

1 - Microelectronic Devices and Circuits Lecture 19 - Differential Amplifier Stages - Outline Announcements Design Problem -coming out tomorrow; PS #10 looks at pieces; neglect the Early effect in large signal analyses Review -Single-transistor building block Stages Common source: general purpose gain stage , workhorse Common gate: small Rin, large Rout, unity Ai, same Aas CSv Source follower: large Rin, small Rout, unity Av, same Ai as CS Series and Shunt feedback: we'll see in special situations Differential Amplifier Stages -Large signal behavior General features: symmetry, inputs, outputs, biasing (Symmetry is the key!)

2 Large signal transfer characteristic Difference- and common-mode signalsDecomposing and reconstructing general signals Half-circuit incremental analysis techniquesLinear equivalent half-circuits Difference- and common-mode analysisExample: analysis of source-coupled pair Clif Fonstad, 11/17/09 Lecture 19 - Slide 1 IBIAS-V+V123 IBIAS-V+V123 Linear Amplifier layouts: The practical ways of puttinginputs to, and taking outputs from, transistors to form linear amplifiers There are 12 choices: three possible nodes to connect to the input, and for each one, two nodes from which to take an output, and two choices of what to do with the remaining node (ground it or connect it to something).

3 Not all these choices work well, however. In fact only three do: Name Input Output Grounded Common source/emitter 123 Common gate/base 321 Common drain/collector 132 (Source/emitter follower) Source/emitter degeneration 1 2 none Clif Fonstad, 11/17/09 Lecture 19 - Slide 2 IBIASV-V+vout+-vin+-CECOIBIASV-V+vout+-v IN+-COCI Three MOSFET single-transistor amplifiers V+ + IBIAS COvin -+ vout -V-SOURCE FOLLOWER Input: gate Output: source Common: drain Substrate: to source IBIASV-V+vin+-CECO vout+-COMMON SOURCE Input: gate Output: drain Common: source Substrate.

4 To source IBIASV-V+vout+-vIN+-COCICOMMON GATE Input: source; Output: drain Common: gate Substrate: to ground vout + -vin + -vout + -vin + -vout + -vin + -Clif Fonstad, 11/17/09 Lecture 19 - Slide 3 Single-transistor amplifiers with feedbackV+ + vin + CO V+ RF CO + voutvout + --vin --RF IBIASIBIAS CE CE V-V-SERIES FEEDBACK PARALLEL FEEDBACK* vout+-vin+-RFClif Fonstad, 11/17/09 vout+-vin+-RF* Also termed "source degeneracy" Lecture 19 - Slide 4 Summary of the single transistor Stages (MOSFET) ! MOSFETV oltagegain, AvCurrentgain, AiInputresistance, RiOutputresistance, RoCommon source"gmgo+gl[]="gmrl'()##ro=1go$ % & ' ( ) Common gate*gm+gmb[]rl'*1*1gm+gmb[]*ro1+gm+gmb+ go[]gt+.

5 / 0 Source followergm[]gm+gmb+go+gl[]*1##1gm+go+gl[ ]*1gmSource degeneracy(series feedback)*"rlRF##*roShunt feedback"gm"GF[]go+GF[]*"gmRF"glGF1GF1"A v[]ro||RF=1go+GF[]$ % & ' ( ) ! Power gain, Ap=Av"AiNote: When vbs = 0 the gmb factors should be deleted. Clif Fonstad, 11/17/09 Lecture 19 - Slide 5 Summary of the single transistor Stages (bipolar) ! BIPOLARV oltagegain, AvCurrentgain, AiInputresistance, RiOutputresistance, RoCommon emitter"gmgo+gl[]="gmrl'()"#glgo+gl[]r$r o=1go% & ' ( ) * Common basegmgo+gl[]=gmrl'()+1+r$#+1[]+#+1[]roE mitter followergm+g$[]gm+g$+go+gl[]+1#glgo+gl[] +#r$+#+1[]rl'rt+r$#+1[]Emitter degeneracy+"rlRF+#+r$+#+1[]RF+roShunt feedback"gm"GF[]go+GF[]+"gmRF"glGF1g$+GF 1"Av[]ro||RF=1go+GF% & ' ( ) * !

6 Power gain, Ap=Av"AiClif Fonstad, 11/17/09 Lecture 19 - Slide 6 -- Differential Amplifiers: emitter- and source-coupled pairs V+ ++ vOUT1 vOUT2 V+ vOUT1 + -vOUT2 + -IBIAS V-++ ++ vIN2vIN1 vIN2 vIN1 ----IBIAS V-Emitter-coupled pair Source-coupled pair Why do we care? -They amplify only difference-mode signals They are easy to interconnect and cascade They help us eliminate coupling capacitors They are optimally suited to integration Clif Fonstad, 11/17/09 Lecture 19 - Slide 7 IBIASvI1vO1+-vO2+-+-vI2+-+-vO-VSS+VDDRDR DM1M2 Differential Amplifiers: large signal analysis of source coupled pairs Source-coupled pair Below: Schematic with resistor loads Right: Large signal equiv.

7 Circuit in saturation Analysis: vI1 - vGS1 +vGS2 -vI2 = 0, vO1 = VDD - RDiD1, vO2 = VDD -RDiD2 KCL at one node: iD1 + iD2 = IBIAS MOSFET relationships: iD1 = K(vGS1-VT)2/2; iD2 = K(vGS2-VT)2/2 (see text for details of analysis) Clif Fonstad, 11/17/09 Lecture 19 - Slide 8 3 KVL loops: Diff. Amps: large signal analysis of source coupled pairs, cont. Results: The outputs again only depend on the difference between the two inputs, (vI1 -vI2): Slope around origin = -gmRD ! vO1=VDD"RD2 KvIN1"vIN2[]2+IBIAS +K2vIN1"vIN2[]4 IBIASK"vIN1"vIN2[]2# $ % & % ' ( % ) % vO2=VDD"RD2 KvIN1"vIN2[]2+IBIAS "K2vIN1"vIN2[]4 IBIASK"vIN1"vIN2[]2# $ % & % ' ( % ) % vO="RDK2vIN1"vIN2[]4 IBIASK"vIN1"vIN2[]2 Symmetrical vo Clif Fonstad, 11/17/09 Only the difference in the inputs matters!

8 ! Lecture 19 - Slide 9 IBIAS+VCCvI1+-vO1+-vO2+-vI2+--VEE+-vORCR CQ2Q1 Differential Amplifiers: large signal analysis ofemitter coupled pairs Emitter-coupled pair Below: Schematic with resistor loads Right: Large signal equivalent circuit in FAR Analysis: 3 KVL loops: vI1 - vBE1 +vBE2 -vI2 = 0, vO1 = VCC - RC FiF1, vO2 = VCC - RC FiF2 KCL at one node: iF1 + iF2 = IBIAS Ideal diode relationships: iF1 IES exp (qvBE1/kT), iF2 IES exp (qvBE2/kT) (see text for details of analysis) Clif Fonstad, 11/17/09 Lecture 19 - Slide 10 Diff. Amps: large signal analysis of emitter coupled pairs, cont.

9 Results: The outputs only depend on the difference between the inputs, (vI1 -vI2): Slope around origin = -gmRC ! vO1=VCC"#FRCIBIAS1+e"qvI1"vI2()kT[]vO2=V CC"#FRCIBIAS1+eqvI1"vI2()kT[]vO="#FRCIBI AS tanhqvI1"vI2()2kTSymmetrical Clif Fonstad, 11/17/09 Only the difference in the inputs matters!! Lecture 19 - Slide 11 _____ Differential Amplifier Analysis -difference-mode and common-mode signals Any pair of signals can be decomposed into a portion that is the identical in both, and a portion that is equal, but opposite in both.

10 For example, if we have two voltages, v1 and v2, we can define a common-mode signal, vC, and a difference-mode signal, vD, as: vC= (v1+ v2)/2 vD= v1- v2 In terms of these two voltages, we can write v1 and v2 as: v1= vC+ vD/2 v2= vC- vD/2 In incremental analysis of linear amplifiers we will decom-pose our inputs into difference-and common-mode inputs: vic = (vin1 + vin2)/2 and vid = vin1 - vin2. We will apply vid to the circuit and get vod (= Avdvid), and then apply vic to the circuit to get voc (= Avcvic). Then we will reconstruct our outputs: vout1 = voc + vod/2 = Avcvic + Avdvid/2 vout2 = voc - vod/2 = Avcvic - Avdvid/2 Clif Fonstad, 11/17/09 Lecture 19 - Slide 12 Differential Amplifier Analysis -incremental analysis exploiting symmetry and superposition vin1+-vin2+-vout1+-vout2+-Linear equivalentcircuit (symmetrical)vin2+-vout2+-vin1+-vout1+-a LEHC: one halfof sym.