Electrical Variability due to Layout Dependent …

1 Electrical Variability due to Layout Dependent Effects: analysis , quantification , and mitigation on 40 and 28nm SOC DesignsMark analysis and Discussions 40nm CMOS Technologya)Transistor variations: Vth, Idsat, Ioffb)Cell timing and leakage 2 Layout Dependent variations (context Dependent ) :LOD,STI, (RTA) Introduction We focus on stress effects including Diffusion Spacing Effects (OSE) and Well Proximity Effects (WPE). Cadence tool LEA is used to analyze stress effects as results of Layout context. Device and cell Variability due to stress are analysed. mitigation strategies for lower systematic Variability are 3 Unintentional stress: LOD and LODeffect is due to mechanical compressive stress induced at boundary of OD.

2 Proportional to the distance to OD boundary. Layout Dependent but not context Dependent . STI becomes compressive as the wafer cools down. The wider STI the higher the stress. Width of STI (Active to Active Spacing) has a strong role in determining the stress. Context 4 Intentional stress: DSL and e SiGe: DSL applies a SiNfilm to create tensile stress on n-and compressive stress on p-MOS. The boundaries of compressive and tensile are synthesized from the well layer. Context Dependent . Well Proximity Effects: WPE MOSclosetowelledgeexhibitsadifferenceinV thandIdsfromthatofthedevicelocatedremote lyfromwelledge. Poly Space Effects (PSE)not context Dependent if cells have dummy polys(1stpolyshave same dimensionsas poly gate), and effectsof 2ndpolysare Stress Effects (Cont.)

3 Well EdgeSC2SC4SC1SC3 Page 5 Library Variability analysis Understand and quantify context Variability Perform quantified area/timing Variability architectural and Layout tradeoffs Prioritize various Layout optimizations or mitigation strategies Optimize selection of context for characterization Device Variability analysis Vthcharacterisation. Idsatcharacterization. Ioffcharacterization. Path Variability analysis analysis of critical paths, Clock Trees, etc More accurate timing analysis and reduce margins3. Variability analysis flowPage 6 LEA path Variability flow: Create data from Encounter Extracts critical cells with context Launch LVS to extract stress effects due to contexts on critical cells Compute delay difference and back-annotate timing LEA path Variability flow is used: To run analysis on critical paths, Clock Trees, etc To provide more accurate timing analysis and reduce margins In Standalone mode or from EncounterEncounterSPEF(x,y)LEF/DEFT iming ViewsSlew/Slack InfoTiming ViewsSlew/Slack InfoTiming ViewsSlew/Slack InfoTiming ViewsSlew/Slack PVT etcSPEF(x,y)SPEF(x,y).

4 SetupSpice Model, DSPF, GDS, Stress setup, etcPVS Stress ExtractionDeltaDelayCalcInstance Slew Delay DerateDelta-Delay CalcDeltaDelayCalcDelta-delay Calc DP for MMMCLEAT iming reportsummaryreport_lde_analysis viewname report_timing_options -max_points10 nworst10 IncrementalSDFC ritical cells with context3. Path VariabilityPage 74. Results : Vthvariability, 40 nmSmall logic cell: Inverter consists of 1 n-MOS and 1 p-MOS1000 random contexts,Top and Bottom: Regular Layout (Filler Cells),Left and Right: Random cells from the , n-MOS, Vds=50mV, T= 40 CFrequency (%)Vthn (V) (%)40nm, p-MOS, Vds= 50mV, T= 40 CVthp (V)VthSpread (mV)Relative Variation (%) , n-MOS, Vds=Vgs= , T= 40 CFrequency (%)Idsatn (mA/ m) (%)40nm, n-MOS, Vds= , Vgs=0, T= 40 CIoffn (pA/ m) , n-MOS, Vds= , T= 40 CVgs (V)Ioff variationIdsat (A)40nm, n-MOS, Vds= , T= 40 CVgs (V)NMOSS preadRelative Variation (%) (mA/ m) (pA/ m) 94.

5 Results:Idsatn, Ioffnvariability, 40 nm4. Results: Idsatp, Ioffpvariability, 40 (%)40nm, p-MOS, Vds=Vgs= , T= 40 CIdsatp (mA/ m) (%)40nm, p-MOS, Vds= , Vgs=0, T= 40 CIoffp (pA/ m) , p-MOS, Vds= , T= 40 CVgs (V)Ioff variationIdsat (A)40nm, p-MOS, Vds= , T= 40 CVgs (V)PMOSS preadRelative Variation (%) (mA/ m) (pA/ m) 104. Results: Cell Variability , 40 nmWorst and best 5 clock tree cells Variability from 40 nm cell libraryCELLSD rive StrengthMax delay spread (%)CELLSD rive StrengthMax Output slew spread (%)CELLSD rive StrengthMax Leakage spread (%) configurationFillerFillerFillerFillerFil lerFillerFillerFillerFillerFillerFillerF illerFillerContext CellsContextCellsVictimFillerPage 114.

6 Discussion: Cell Variability , 40 nmSmaller cells demonstrate higher Variability and bigger cells have lower Variability as shown in the above Variability is affected mostly (Percentage) (WPEandOSEatlateraleffects). (smallerOSEV erticaleffects).Page 12 28nm MOSFETs Variability due to stress. Vthand IdsatVariability of n-MOS increase with technology scaling. Ioffvariability is much smaller. Variability of p-MOS is about half of 40nm devices, which may be because of DSL and SiGetechnologies. Up to 4% of timing and of leakage Variability of cells are found. The 28nm technology is better than 40nm according to context Dependent Variability . 135. 28nm devicesWorst and best 5 clock tree cells timing and leakage variations from 28 nm cell libraryCell Variability at 28nm technology is smaller than that of 40nm StrengthMax delay spread (%)CELLSD rive StrengthMax Output slew spread (%)CELLSD rive StrengthMax Leakage spread (%) Results of 28nm devices Cell variabilityPage 146.

7 Possible mitigation Strategies IDSATD ummy ODMin (mA/ m)Max (mA/ m)Variation (%)NMOSWith (OSE) 15 Biggerverticaldiffusionspacingisgoodforp -MOScurrent, :Makingthetopcontextcellsalittlefartherf romthevictim. Deviceperformancebenefitsfromsmallerhori zontaldiffusionspacing:Strategy3 (WPE) Thesmallerdistancefromgatetowelledges, diagram of physical distances between gate to well (PSE) Possible mitigation Strategies (Cont.) IDSATD ummy PolyMin (mA/ m)Max (mA/ m)Variation (%)NMOSWith 167. Dependent stress effects (Oxide Spacing, Well Proximity Effects) are significant for nanodevices and cell is used for device, cell, circuit Variability analysis due to MOSFET Variability due to stress are Variability of 40nm due to stress are affecting SOC strategies to reduce context Dependent MOSFETs Variability due to context Dependent Variability at 40 and 28nm 17 work was supported by a Knowledge Transfer Secondment, funded by the Engineering and Physical Sciences Research CouncilThanks to:YangangWang, Andrew Appleby, Mark Scoones, Sonia Caldwell, TouqeerAzam, Philippe Huratand Chris Pitchford18