etri-asic design intro - pldworld.com

1 ETRIASIC ASIC 2 ETRIASIC r r ASIC IC , What is ASIC?, Why ASIC? What is Semiconductor?, ASIC ? ? ASIC ? ASIC 3 ETRIASIC r r , ASIC , , 1996 , VLSI , , 1997 7 , Surviving the ASIC Experience, Prentice Hall, 1992 Douglas J Smith, HDL Chip design , Doone Publications, 1996 D. A. Pucknell et al, Basic VLSI design , Prentice Hall, 1994 T. Williams., VLSI Testing, North-Holland Publishers, 1986 Watts, , Submicron Integrated Circuits, John Wiley and Sons Inc.

2 , New York, 1989 Sze, S. M., Semiconductor Devices: Physics And Technology, Bell Telephone Laboratories, USA., 1985 Douglas J Smith, HDL Chip design , DoonePublications, USA., 19964 ETRIASIC ASIC rIC Standard IC Memory Microprocessor DSP TTL ASIC( Custom IC) Full Custom Semi-Custom-SOG(Sea Of Gate)-CBIC(Cell Base IC Standard Cell) PLD-SPLD: PAL(Programmable Array of Logics)-CPLD: PAL-FPGA(Field Programmable Gate Array) ASSP SOC(System On a Chip) : IP(Intellectual Property) 5 ETRIASIC ASIC rWhat is ASIC?

3 Application Specific Integrated Circuit System IC Non-MemeoryIC Implementation of an Application Specific Algorithm on a Silicon Many Definitions Possible(Software ) SoC(System on a Chip) -Level0-Level1-Level2-Level36 ETRIASIC ASIC rWhy ASIC? Cost Reduction Area Reduction Protecting IP High Performance High Reliability Low Power Consumption7 ETRIASIC ASIC rWhat is Semiconductor? Conductor Insulator Semiconductor Energy Gap-Si: , Ge: Electron-Hole Pair PN Junction(Diode) PNP(or NPN) Transistor-Bipolar Transistor-CMOS Transistor-BiCMOST ransistor-Compound Material Transistor.

4 MESFET8 ETRIASIC ASIC r P6P5i860i486i80286HP32i43201i8087i8086i8 080i4004 1041051061077570808590952000 10510610710810964K256K1M4M16M64M256 MDRAM / 9 ETRIASIC ASIC r Hierachical Representation Top-down Bottom-up(library-base) BACDEFGHHJIJ10 ETRIASIC ASIC r (a) C #include < >main( ){ int input,ouput; .. output=!input; ..} 0110(b) VinvVin(c) Vout (e) (f) (d) 11 ETRIASIC ASIC r ?

5 ? ASIC ? Digital ASIC ? Analog ASIC ? IP ? Application System ? I/O Pin ?rASIC ? ASIC Foundry ? ASIC Test ? ASIC ? ASIC Tool ? ASIC Foundry design Kit ? Performance Technology ?12 ETRIASIC ASIC rASIC Chip Chip Chip Proto-Type Chip 13 ETRIASIC ASIC rASIC design Flow(Front-End)ASIC VHDL CodingVHDL SimulationSynthesisTest Vector SimulationSchematic EntryTest Vector SimulationVerified Netlist14 ETRIASIC ASIC rASIC design Flow(Back-End)Verified Verified NetlistNetlistP&R Seed FileP&R Seed FileP&RP&RCap.

6 Net. ExtractCap. Net. ExtractPostPost--SimulationSimulationMer ge PhantomMerge PhantomDRC, LVSDRC, LVSGDS FileGDS File15 ETRIASIC ASIC rASIC Chip Mask MASK : : : ASIC CIFGDS MEBESMASK ToolCATSDRACULAMASK 16 ETRIASIC ASIC r 3 1.. CVD(Chemical Vapor Deposition) : Poly-Silicon, , , ( ), PSG(Phosphorus Silica Glass). PVD(Physical Vapor Deposition) : Al, Silicide 2. Photo Etch . Lithography -Photo Resist - (Expose) : UV - (Develop)-Photo Resist : (Negative Resist ).

7 Etch - -Photo Resist 3.. : (900-1000C) (Furnace) . 17 ETRIASIC ASIC MOSFET 1. Wafer 2. : 3. Channel Stop (NMOSFET B )4. LOCOS ( )5. 6. (SiO2) 7. Threshold Voltage Control 8. ( Poly-Silicon )9. 10. Source, Drain 11. Metal 12. Contact 13. 1st Metal 14. 1st Metal to 2nd Metal 15. 2nd Metal Via 16. 2nd Metal 17. (Passivation) 18.

8 Pad 19. Wafer Test Line 20. Inking Sawing21. Package Line 22. Package Test Metal 1, 2 Al 3 , 4 18 ETRIASIC ASIC rASIC ASIC Military Industrial Commercial ASIC ASIC Tool ASIC Chip (Full Custom, CBIC, SOG) (Macro Cell, Mega-Cell) ( design Rule) Package System System Block Diagram System Description ASIC Block ASIC Block Diagram ASIC Description Timing(Truth Table)19 ETRIASIC ASIC - -Voltage Level-Pull Up/Pull Down - -Input Level-Reference Signal (Reference Signal )-Setup Time Margin-Hold Time Margin-Package Pin Number-Die Pad Number-Active (Active Low?)

9 , Active High?)- Pad Cell Name -Output Level-Propagation Delay -Sink Current-Source Current-Open Drain/Collector -Tristate -Package Pin Number-Die Pad Number- Pad Cell Name20 ETRIASIC ASIC (BiDirectional) -Control (Control Mode(I/O)?)-Input, Output Level-Sink Current-Source Current-Propagation Delay-Package Pin Number-Die Pad Number-Tristate?-Open Drain/Collector?- Pad Cell Name Clock -Asynchronous Clock -Clock -Clock Duty Cycle-Crystal Type Oscillator Type -Package Pin Number-Die Pad Number 21 ETRIASIC ASIC rTestable design Testability.

10 Test Vector Fault Cover Controllability -Clock Signals-Control Signals(Preset, Clear, Enable, Hold)-Select Signals(Data Select, Data Bus, Address Bus) Observability -Control Signals-Data Lines of Storage Devices(Flip Flops, Counters, Shift Register, RAM, ROM)-Global Feedback Path-Data Output of Combinational Logic Devices(Encoders, Multiplexers, Parity Generators) DFT( design For Testability) Ad-Hoc DFT Techniques : Testability Test Circuit 1) Test Points : Decoder, Multiplexer, Shift Register design Testable design .