First Time, Every Time Practical Tips for Phase- Locked ...

1 First time , Every time . Practical tips for Phase- Locked Loop Design Dennis Fischette Email: Website: Copyright, Dennis Fischette, 1. 2009. Outline Introduction Basic Feedback Loop Theory Jitter and Phase Noise Common Circuit Implementations Circuit Verification Design for Test Copyright, Dennis Fischette, 2. 2009. Introduction Copyright, Dennis Fischette, 3. 2009. How Are PLL s Used? Frequency Synthesis ( generating a 1 GHz clock from a 100 MHz reference in a CPU). Skew Cancellation ( Phase- aligning an internal clock to the I/O clock) (May use a DLL instead).

2 Copyright, Dennis Fischette, 4. 2009. How Are PLL s Used? Extracting a clock from a random data stream ( serial- link clock-data recovery). Reference Clean-Up ( low-pass filter source-synchronous clock in high-speed I/O). Frequency Synthesis is the focus of this course. Design Priority? Frequency and/or phase accuracy? Copyright, Dennis Fischette, 5. 2009. What is a PLL? Negative feedback control system where fout tracks fin and rising edges of input clock align to rising edges of output clock Mathematical model of frequency synthesizer fin fout . Phase- Vin t sin 2 fin t Locked Vout t sin 2 Nfint Loop Phase = frequency 1 df t.

3 F t 2 f t dt f t . 2 dt When phase- Locked , fout Nfin f out Nfin Copyright, Dennis Fischette, 6. 2009. Charge-Pump PLL Block Diagram GoFaster RefClk Phase- Charge Vctl Level- ClkOut Freq VCO. Pump VCO Shifter Detector GoSlower C1 C2. Feedback FbClk Div Sampled-system ( Phase- error is input variable). Phase error is corrected by changing frequency (f(t) = f(t) dt). Resistor provides means to separate correction of frequency error from correction of phase error Copyright, Dennis Fischette, 7. 2009. PLL Circuit Diagram Copyright, Dennis Fischette, 8. 2009. PLL Circuit Diagram Observations Under-damped PLL - ringing Effect of cycle slips on Vctl Net integrating cap voltage Vc1 lags control voltage Vctl Copyright, Dennis Fischette, 9.

4 2009. Components in a Nutshell Phase- Frequency Detector (PFD): outputs digital pulse whose width is proportional to sampled phase error Charge Pump (CP): converts digital error pulse to analog error current Loop Filter (LPF): integrates (and low-pass filters in continuous time ) the error current to generate VCO control voltage VCO: low-swing oscillator with frequency proportional to control voltage Level Shifter (LS): amplifies VCO levels to full-swing Feedback Divider (FBDIV): divides VCO clock to generate FBCLK clock for phase comparison w/reference Copyright, Dennis Fischette, 10.

5 2009. PLL Feedback Loop Theory Copyright, Dennis Fischette, 11. 2009. What Does PLL Bandwidth Mean? PLL acts as a low-pass filter with respect to the reference modulation. High-frequency reference jitter is rejected Low-frequency reference modulation ( , spread-spectrum clocking) is passed to the VCO clock PLL acts as a high-pass filter with respect to VCO jitter Bandwidth is the modulation frequency at which the PLL. begins to lose lock with the changing reference (-3dB). Fout lower BW. Fout BW. Fref BW. rejects Fvco higher BW. ref noise rejects VCO noise log(frequency) log(frequency).

6 Copyright, Dennis Fischette, 12. 2009. Closed-Loop PLL Transfer Function Transfer function describes how PLL responds to excess . reference phase. RefClk phase modulation Analyze PLL feedback in frequency-domain Phase is state variable, not frequency s is the reference modulation frequency, not reference oscillation frequency Assumes continuous- time (not sampled) behavior ffb = (fref - ffb) * G(s) where G(s) == open-loop gain H(s) = ffb/fref = G(s)/(1+G(s)). Copyright, Dennis Fischette, 13. 2009. Open-Loop PLL Gain G(s) = (Kvco/s)IcpF(s)*e-sTd/M. where ferr Kvco = VCO gain in Hz/V.

7 Icp = charge pump current in Amps F(s) = loop filter transfer function in Volt/Amp M = feedback divisor Td = delay in feedback-loop ( FBDIV, Tpfd/2). Copyright, Dennis Fischette, 14. 2009. PLL Components in Frequency Domain (1+s*rc1). Vctl(s) / Icp(s) =. s*( (c1+c2)+(s*rc1*c2). Charge Pump f ref f err Vctl f vco sub Icp/2pi Kvco/s PFD VCO. C1 C2. ffb 1/N. FBDIV. Copyright, Dennis Fischette, 15. 2009. Closed-loop PLL Transfer Function H(s) = n2 (1+ s/ z) / (s2+2s n + n2). where n = undamped natural frequency (rad/s). z = stabilizing zero = 1 /RC1 (rad/s). = damping factor 2nd-order (two poles p1,p2 and one zero).)

8 2nd-order ignores C2 cap and feedback delays If < 1, complex poles lead to damped oscillation Real exponential decay( n) , Imag oscillation ( n). If > 1, z and p1 cancel: BW(-3dB) ~ 2 n Acts like single-pole system Copyright, Dennis Fischette, 16. 2009. What is a Zero ? The Zero in the numerator of the closed-loop transfer function is the frequency in radians/s where the gain of the integral and proportional paths are equal. Classic loop: z = 1 /RC1 (rad/s). Concept can be applied to loop filters that do not contain a resistor. Copyright, Dennis Fischette, 17.

9 2009. Natural Frequency Related to bandwidth n = (2 * BW) / sqrt( 1+2 2+sqrt( (1+2 2)2+1 ) ). Undamped Natural Frequency: n = sqrt(Kvco*Icp/( M*C1)) in rad/sec where Kvco = VCO gain in Hz/V. Icp = charge pump current in Amps M = feedback divisor C1 = large LPF capacitor For stability: n/2 < ~1/15 reference frequency Typical value: 500 kHz < n/2 < 10 MHz Copyright, Dennis Fischette, 18. 2009. Damping Factor Related to stability Damping Factor: = Rlpf * C1 * n /2. Dimensionless, Usually ~ < < ~2. Lower end of range for low period jitter Higher end of range for accurate ref phase tracking Rlpf provides means to set stability independent of bandwidth Copyright, Dennis Fischette, 19.

10 2009. Open-Loop Transfer Function 20*log(Gain) vs. log(Modulation Frequency). 2 poles @ origin, 1 zero @ wz, 1 pole @wp -40dB/dec Open-Loop Gain (dB). -20dB/dec log(wmod). wz wn wc wp -40dB/dec wz = 1/RC1. wp = 1/RC2. wc = crossover frequency wn = natural frequency Copyright, Dennis Fischette, 20. 2009. Stability and Phase Margin Phase margin determines stability as in other feedback loops 180 - phase of open-loop transfer function at crossover frequency fm (degrees) = (180/ )*(atan( c*RC1) atan( c*RC2)- c*Tdly). c == crossover frequency frequency where open-loop gain G(s) = 0dB.