Floating-Point Operator v7 - Xilinx

1 Floating-Point Operator IP Product GuideVivado design SuitePG060 December 16, 2020 Floating-Point Operator December 16, of ContentsIP FactsChapter 1: OverviewNavigating Content by design Process .. 2 Core Overview .. 2 Unsupported Features .. 2 Licensing and Ordering .. 3 Chapter 2: Product SpecificationStandards .. 4 Performance .. 6 Resource Utilization .. 7 Port Descriptions .. 8 Chapter 3: Designing with the CoreGeneral design Guidelines .. 14 Accumulator design Guidelines .. 17 Clocking.

2 19 Resets .. 20 Protocol Description .. 20 Chapter 4: design Flow StepsCustomizing and Generating the Core .. 28 Constraining the Core .. 38 Simulation .. 39 Synthesis and Implementation .. 39 Chapter 5: C ModelFeatures .. 40 Overview .. 40 Unpacking and Model Contents .. 41 Installation .. 42C Model Interface.. 42 Compiling .. 62 Send FeedbackFloating-Point Operator December 16, .. 63 Dependent Libraries .. 64 Example .. 65 Chapter 6: Test BenchDemonstration Test Bench.

3 67 Appendix A: UpgradingMigrating to the vivado design suite .. 69 Upgrading in the vivado design suite .. 69 Appendix B: DebuggingFinding Help on .. 73 Debug Tools .. 74 Simulation Debug.. 75 AXI4-Stream Interface Debug .. 75 Appendix C: Additional Resources and Legal NoticesXilinx Resources .. 76 Documentation Navigator and design Hubs .. 76 References .. 76 Revision History .. 77 Please Read: Important Legal Notices .. 78 Send FeedbackFloating-Point Operator December 16, SpecificationIntroductionThe Xilinx Floating-Point Operator core provides you with the means to perform Floating-Point arithmetic on an FPGA.

4 The core can be customized for operation, wordlength, latency and Supported operators: Multiply Add/subtract Accumulator Fused multiply-add Divide Square-root Comparison Reciprocal Reciprocal square root Absolute value Natural logarithm Exponential Conversion from Floating-Point to fixed-point Conversion from fixed-point to Floating-Point Conversion between Floating-Point types Unfused multiply-add Unfused multiply-accumulator Accumulator primitive Compliance with IEEE-754 Standard [Ref 1] (with only minor documented deviations)

5 Parameterized fraction and exponent wordlengths for most operators Optimizations for speed and latency Fully synchronous design using a single clockIP FactsLogiCORE IP Facts TableCore SpecificsSupported Device Family(1)UltraScale+ UltraScale Versal ACAPZynq -7000 SoC7 SeriesSupported User InterfacesAXI4-StreamResourcesPerformanc e and Resource Utilization webpageProvided with CoreDesign FilesEncrypted RTLE xample DesignNot ProvidedTest BenchVHDLC onstraints FileNot ProvidedSimulation ModelEncrypted VHDL, C ModelSupported S/W DriverN/ATested design Flows(2) design EntryVivado design SuiteSystem Generator for DSPS imulationFor supported simulators, see theXilinx design Tools.

6 Release Notes SynthesisSupportRelease Notes and Known IssuesAR: 54504 All vivado IP Change LogsMaster vivado IP Change Logs: 72775 Xilinx Support web pageNotes: 1. For a complete listing of supported devices, see the vivado IP For the supported versions of third-party tools, see theXilinx design Tools: Release Notes FeedbackFloating-Point Operator December 16, 1 OverviewNavigating Content by design ProcessXilinx documentation is organized around a set of standard design processes to help you find relevant content for your current development task.

7 This document covers the following design processes: Hardware, IP, and Platform Development: Creating the PL IP blocks for the hardware platform, creating PL kernels, subsystem functional simulation, and evaluating the vivado timing, resource and power closure. Also involves developing the hardware platform for system integration. Topics in this document that apply to this design process include: Port Descriptions Clocking Resets Customizing and Generating the Core C ModelCore OverviewThe Xilinx Floating-Point Operator core allows a range of Floating-Point arithmetic operations to be performed on FPGA.

8 The operation is specified when the core is generated, and each operation variant has a common interface. This interface is shown in Figure 2-1. Unsupported FeaturesSee FeedbackFloating-Point Operator December 16, 1:OverviewLicensing and OrderingThis Xilinx LogiCORE IP module is provided at no additional cost with the Xilinx vivado design suite under the terms of the Xilinx End User License. Information about this and other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual Property page.

9 For information about pricing and availability of other Xilinx LogiCORE IP modules and tools, contact your local Xilinx sales FeedbackFloating-Point Operator December 16, 2 Product SpecificationStandardsIEEE-754 SupportThe Xilinx Floating-Point Operator core complies with much of the IEEE-754 Standard [Ref 1]. The deviations generally provide a better trade-off of resources against functionality. Specifically, the core deviates in the following ways: Non-Standard Wordlengths Denormalized Numbers Rounding Modes Signaling and Quiet NaNsNon-Standard WordlengthsThe Xilinx Floating-Point Operator core supports a different range of fraction and exponent wordlength than defined in the IEEE-754 Formats: binary16 (Half Precision Format) Uses 16 bits, with an 11-bit fraction and 5-bit exponent.

10 Binary32 (Single Precision Format) Uses 32 bits, with a 24-bit fraction and 8-bit exponent. binary64 (Double Precision Format) Uses 64 bits, with a 53-bit fraction and 11-bit exponent. binary128 (Quadruple Format) not supportedExtendable Precision Formats (not available on all operators): Uses up to 80 bits. Exponent width of 4 to 16 FeedbackFloating-Point Operator December 16, 2:Product Specification Fraction width of 4 to 64 bits Note:Limitations apply based on exponent width. See the vivado Integrated design Environment for actual NumbersThe exponent limits the size of numbers that can be represented.