Fully integrated CMOS power amplifier design using the ...

1 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 3, MARCH 2002371 Fully integrated CMOS power amplifier DesignUsing the distributed Active-TransformerArchitectureIchiro Aoki, Student Member, IEEE, Scott D. Kee, David B. Rutledge, Fellow, IEEE, and Ali Hajimiri, Member, IEEEA bstract A novel on-chip impedance matching and power -combining method, thedistributed active transformeris combines several low- voltage push pull amplifiers efficientlywith their outputs in series to produce a larger output power whilemaintaining a 50- match. It also uses virtual ac grounds andmagnetic couplings extensively to eliminate the need for any off-chip component, such as tuned bonding wires or external induc-tors.

2 Furthermore, it desensitizes the operation of the amplifier tothe inductance of bonding wires making the design more repro-ducible. To demonstrate the feasibility of this concept, a 2-V truly Fully integrated power amplifier with 50- inputand output matching has been fabricated using CMOS transistors. It achieves a power added efficiency (PAE) of 41% atthis power level. It can also produce 450 mW using a 1-V suppression is 64 dBc or better. This new topologymakes possible a truly Fully integrated watt-level gigahertz rangelow- voltage CMOS power amplifier for the first Terms Circular geometry, CMOS analog integrated cir-cuit, distributed active transformer, double differential, harmoniccontrol, impedance transformation, low voltage , power amplifier , power INTRODUCTIONTHE design of a Fully integrated power amplifier with areasonable output power , efficiency, and gain remains oneof the major challenges in today s pursuit of a single-chip inte-grated transceiver.

3 Although several advances have been madein this direction, a truly Fully integrated CMOS power amplifierat watt level output power has not been reported to this external components such as bonding wires andexternal baluns have been used as tuned elements to produceoutput power levels in excess of 1 W using CMOS [1], [2] orSi-Bipolar transistors [3], [4]. Alternative technologies withhigher breakdown voltage devices or higher substrate resistivityhave been used to increase the output power and efficiency ofintegrated amplifiers. In particular, LDMOS transistors with abreakdown voltage of 20 V [5] and GaAs monolithic microwaveintegrated circuits (MMICs) with semi-insulating substrate[6] [8] have been used to integrate power amplifiers.

4 To date, thehighest power levels achieved with Fully integrated amplifiersin standard silicon are on the order of 100 mW [9], [10].Manuscript received July 23, 2001; revised October 19, 2001. This work wassupported in part by the Lee Center for Advanced Networking, Intel Corpora-tion, the Army Research Office, Jet Propulsion Laboratory, Infineon, and theNational Science authors are with the California Institute of Technology, Pasadena, CA91125 USA (e-mail: Item Identifier S 0018-9200(02) main obstacles in the design of a Fully integrated CMOS power amplifier are the low drain gate, drain source, anddrain substrate breakdown voltages of the transistor and thelow resistivity of the substrate.)

5 The low breakdown voltagelimits the output power and the low substrate resistivity reducesamplifier s power efficiency. These problems are exacerbatedas the CMOS transistor s minimum feature size is scaled downfor faster operation resulting in lower substrate resistivity andsmaller breakdown achieve a larger output power despite the low transistorbreakdown voltage , some form of impedance transformation isnecessary. This impedance transformation could be achievedusing an ideal 1 :transformer. Unfortunately, an on-chipspiral 1 :transformer on a standard CMOS substrate is verylossy and will degrade the performance of the amplifier greatly[11] [13].

6 An on-chip resonant match presents a lower, yet sig-nificant, loss [13]. This problem becomes worse as the desiredpower level increases and/or the transistor breakdown voltagedecreases. Another difficulty presented by these methods isthe thermal dissipation. By not using any means of powercombining, the active device is concentrated in one place,resulting in a higher junction temperature that can lower thelong-term reliability or even damage the paper describes anovel distributed active-transformerpower amplifier (DAT) as an alternative and efficient methodof impedance transformation and power combining to achievea high output power while maintaining an acceptable powerefficiency.

7 It overcomes the low breakdown voltage of short-channel MOS transistors and thermal dissipation problems. Thisnew circular geometry can be used to implement linear classesA, AB, and B, as well as the switching mode E/F family [14]of push pull switching power amplifiers. Details of the passiveimpedance transformation and power -combining network com-paring its efficiency to the conventional methods are presentedin a companion paper [13]. Section II explains in more detail thechallenges in designing a power amplifier using CMOS tech-nology. In Section III, the design evolution leading to the DATpower amplifier is described.

8 Section IV gives a detailed insightabout classes of operations, which might be used with the results are presented in Section CHALLENGES ININTEGRATEDPOWERAMPLIFIERSS everal problems arise when using submicron CMOS tech-nology without any off-chip components or wire-bond induc-tors for watt-level Fully integrated power amplifiers. design is-0018 9200/02$ 2002 IEEE372 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 3, MARCH 2002 Fig. diagram of a power amplifier with critical points for of a power amplifier are described here to illustrate theseproblems. Fig. 1 shows a simplified diagram of a power ampli-fier with its key terms of frequency response, today s submicron CMOSand/or Si-bipolar technologies offer very acceptable n-channelor n-p-n transistors ( ,andof CMOS tran-sistors reach up to 80 GHz).

9 If the only limitation is transistor sspeed and gain, in principle it is possible to design switching orlinear-mode amplifiers up to the 20 GHz range. Unfortunately,low breakdown voltages and high knee voltages,1, of thetransistors limit the maximum voltage swing at their drainsor collectors. This voltage swing limitations make a largeimpedance transformation necessary in order to deliver anypower beyond 100 mW to 50-loads,. This can be seenfrom the following calculations for a knee voltage of V andsupply voltage of 3 V:VmW(1)Another issue is the drain impedance control at the funda-mental frequency and at the harmonic frequencies taking intoaccount the transistor parasitic capacitances.

10 Impedance con-trol is required to achieve the desired harmonic suppressionsat the output and to improve the drain wave shaping for betterpower efficiency [15]. This harmonic control must incorporatean inductor, in order to achieve a high-frequency selectivity andto resonate the transistor drain capacitance, as may be seen inthe block diagram of the hypothetical power amplifier shownin Fig. 1. Even in class-A operation, in order to satisfy the rigidwireless communications standards, it is necessary to have someharmonic suppression to offset the transistor nonlinearity pre-sented when the power amplifier is operating near its gain com-pression to the series metal resistance and induced currents in sub-strate, the on-chip harmonic rejection inductor presents a verylow quality factor.