HSPICE Elements and Device Models Manual

1 HSPICE Elements and Device Models ManualVersion , September 2005iiHSPICE Elements and Device Models Notice and Proprietary InformationCopyright 2005 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary information that is the property of Synopsys, Inc. The software and documentation are furnished under a license agreement and may be used or copied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced, transmitted, or translated, in any form or by any means, electronic, mechanical, Manual , optical, or otherwise, without prior written permission of Synopsys, Inc., or as expressly provided by the license to Copy DocumentationThe license agreement with Synopsys permits licensee to make copies of the documentation for its internal use only. Each copy shall include all copyrights, trademarks, service marks, and proprietary rights notices, if any.

2 Licensee must assign sequential numbers to all copies. These copies shall contain the following legend on the cover page: This document is duplicated with the permission of Synopsys, Inc., for the exclusive use of _____ and its employees. This is copy number _____. Destination Control StatementAll technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader s responsibility to determine the applicable regulations and to comply with , INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR Trademarks ( )Synopsys, AMPS, Arcadia, C Level Design, C2 HDL, C2V, C2 VHDL, Cadabra, Calaveras Algorithm, CATS, CSim, Design Compiler, DesignPower, DesignWare, EPIC, Formality, HSPICE , Hypermodel, iN-Phase, in-Sync, Leda, MAST, Meta, Meta-Software, ModelTools, NanoSim, OpenVera, PathMill, Photolynx, Physical Compiler, PowerMill, PrimeTime, RailMill, RapidScript, Saber, SiVL, SNUG, SolvNet, Superlog, System Compiler, Testify, TetraMAX, TimeMill, TMA, VCS, Vera, and Virtual Stepper are registered trademarks of Synopsys, ( )

3 AbraCAD, abraMAP, Active Parasitics, AFGen, Apollo, Apollo II, Apollo-DPII, Apollo-GA, ApolloGAII, Astro, Astro-Rail, Astro-Xtalk, Aurora, AvanTestchip, AvanWaves, BCView, Behavioral Compiler, BOA, BRT, Cedar, ChipPlanner, Circuit Analysis, Columbia, Columbia-CE, Comet 3D, Cosmos, CosmosEnterprise, CosmosLE, CosmosScope, CosmosSE, Cyclelink, Davinci, DC Expert, DC Expert Plus, DC Professional, DC Ultra, DC Ultra Plus, Design Advisor, Design Analyzer, Design Vision, DesignerHDL, DesignTime, DFM-Workbench, Direct RTL, Direct Silicon Access, Discovery, DW8051, DWPCI, Dynamic-Macromodeling, Dynamic Model Switcher, ECL Compiler, ECO Compiler, EDAnavigator, Encore, Encore PQ, Evaccess, ExpressModel, Floorplan Manager, Formal Model Checker, FoundryModel, FPGA Compiler II, FPGA Express, Frame Compiler, Galaxy, Gatran, HDL Advisor, HDL Compiler, Hercules, Hercules-Explorer, Hercules-II, Hierarchical Optimization Technology, High Performance Option, HotPlace, HSPICE -Link, iN-Tandem, Integrator, Interactive Waveform Viewer, i-Virtual Stepper, Jupiter, Jupiter-DP, JupiterXT, JupiterXT-ASIC, JVXtreme, Liberty, Libra-Passport, Library Compiler, Libra-Visa, Magellan, Mars, Mars-Rail, Mars-Xtalk, Medici, Metacapture, Metacircuit, Metamanager, Metamixsim, Milkyway, ModelSource, Module Compiler, MS-3200, MS-3400, Nova Product Family, Nova-ExploreRTL, Nova-Trans, Nova-VeriLint, Nova-VHDL lint, Optimum Silicon, Orion_ec, Parasitic View, Passport, Planet, Planet-PL, Planet-RTL, Polaris, Polaris-CBS, Polaris-MT, Power Compiler, PowerCODE, PowerGate, ProFPGA, ProGen, Prospector, Protocol Compiler, PSMGen, Raphael, Raphael-NES, RoadRunner, RTL Analyzer, Saturn, ScanBand, Schematic Compiler, Scirocco, Scirocco-i, Shadow Debugger, Silicon Blueprint.

4 Silicon Early Access, SinglePass-SoC, Smart Extraction, SmartLicense, SmartModel Library, Softwire, Source-Level Design, Star, Star-DC, Star-MS, Star-MTB, Star-Power, Star-Rail, Star-RC, Star-RCXT, Star-Sim, Star-SimXT, Star-Time, Star-XP, SWIFT, Taurus, TimeSlice, TimeTracker, Timing Annotator, TopoPlace, TopoRoute, Trace-On-Demand, True- HSPICE , TSUPREM-4, TymeWare, VCS Express, VCSi, Venus, Verification Portal, VFormal, VHDL Compiler, VHDL System Simulator, VirSim, and VMC are trademarks of Synopsys, Marks (SM)MAP-in, SVP Caf , and TAP-in are service marks of Synopsys, is a trademark of the Open SystemC Initiative and is used under and AMBA are registered trademarks of ARM other product or company names may be trademarks of their respective owners. Printed in the Elements and Device Models Manual , Elements and Device Models This Manual ..xiThe HSPICE Documentation Set.

5 XiiSearching Across the Entire HSPICE Documentation Set ..xiiiOther Related Publications ..xivConventions ..xivCustomer Support .. of Models ..1 Using Models to Define Netlist Elements ..2 Supported Models for Specific Simulators ..3 Selecting Models ..3 Subcircuits .. Device Models ..7 Resistor Device Model and Equations ..8 Wire RC Model ..8 Wire RC Model Parameter Syntax ..10 Resistor Syntax ..11 Resistor Model Selector ..11 Resistor Model Equations ..12 Wire Resistance Calculation ..12 Wire Capacitance Calculation ..13 Resistor Noise Equation..14 Resistor Temperature Equations ..15 Noise Parameter for Resistors ..15 Capacitor Device Model and Equations ..16 Capacitance Model ..16 Parameter Limit Checking ..17ivHSPICE Elements and Device Models Device Equations ..17 Effective Capacitance Calculation ..18 Capacitance Temperature Equation ..19 Inductor Device Model and Equations.

6 19 Inductor Core Models ..20 Inductor Device Equations ..23 Checking Parameter Limits ..23 Inductor Temperature Equation ..24 Jiles-Atherton Ferromagnetic Core Model ..25 Input File..27 Plots of the b-h Curve..27 Discontinuities in Inductance Due to Hysteresis ..28 Input File..29 Plots of the Hysteresis Curve and Inductance ..29 Optimizing the Extraction of Parameters ..29 Input File..31 Diode Types ..32 Using Diode Model Statements ..33 Setting Control Options ..33 Bypassing Latent Devices ..34 Setting Scaling Options ..34 Using the Capacitor Equation Selector Option DCAP ..34 Using Control Options for Convergence ..34 Specifying Junction Diode Models ..35 Using the Junction Model Statement ..36 Using Junction Model Parameters ..37 Geometric Scaling for Diode Models ..43 LEVEL=1 Scaling ..43 LEVEL=3 Scaling ..43 Defining Diode Models ..45 Diode Current ..45 Using Diode Equivalent Circuits.

7 45 Determining Temperature Effects on Junction Diodes ..47 Using Junction Diode Equations ..50 Using Junction DC Equations ..51 Forward Bias: vd > -10 vt ..51 Reverse Bias: BVeff < vd < -10 vt..52 Breakdown: vd < - BV..52 HSPICE Elements and Device Models Bias ..53 Reverse Bias ..53 Using Diode Capacitance Equations ..54 Using Diffusion Capacitance Equations ..54 Using Depletion Capacitance Equations ..54 Metal and Poly Capacitance Equations (LEVEL=3 Only)..55 Using Noise Equations..55 Temperature Compensation Equations ..56 Energy Gap Temperature Equations ..56 Leakage Current Temperature Equations ..56 Tunneling Current Temperature Equations ..57 Breakdown-Voltage Temperature Equations ..57 Transit-Time Temperature Equations ..57 Junction Built-in Potential Temperature Equations ..57 Junction Capacitance Temperature Equations ..58 Grading Coefficient Temperature Equation.

8 59 Resistance Temperature Equations ..59 Using the JUNCAP Model ..59 Theory ..63 JUNCAP Model Equations ..65 Nomenclature ..65ON/OFF Condition ..67DC Operating Point Output..67 Temperature, Geometry and Voltage Dependence ..68 JUNCAP Capacitor and Leakage Current Model ..69 Using the Fowler-Nordheim Diode ..72 Fowler-Nordheim Diode Model Parameters LEVEL=2 ..72 Using Fowler-Nordheim Diode Equations ..73 Fowler-Nordheim Diode Capacitances..73 Converting National Semiconductor Models ..73 Using the Scaled Diode Subcircuit Definition ..74DC Operating Point Output of Diodes .. and MESFET Models ..75 Overview of JFETs..76 Specifying a Model..77 Bypassing Latent Devices ..77 Overview of Capacitor Model..79 Model Applications ..79 Convergence ..80viHSPICE Elements and Device Models Equations ..80 JFET and MESFET Equivalent Circuits ..80 Scaling ..80 JFET Current Conventions.

9 81 JFET Equivalent Circuits ..81 Transconductance ..82 Output Conductance ..82 JFET and MESFET Model Statements ..86 JFET and MESFET Model Parameters ..86 ACM (Area Calculation Method) Parameter Equations ..94 JFET and MESFET Capacitances ..96 Gate Capacitance CAPOP=0 ..96 Gate Capacitance CAPOP=1 ..98 Gate Capacitance CAPOP=2 ..99 Capacitance Comparison (CAPOP=1 and CAPOP=2) ..100 JFET and MESFET DC Equations..101DC Model Level 1 ..101DC Model Level 2 ..102DC Model Level 3 ..102 JFET and MESFET Noise Models ..104 Noise Equations ..104 For NLEV = 3 ..105 JFET and MESFET Temperature Equations ..106 Temperature Compensation Equations ..108 Energy Gap Temperature Equations ..108 Saturation Current Temperature Equations ..109 Gate Capacitance Temperature Equations ..109 Threshold Voltage Temperature Equation ..110 Mobility Temperature Equation ..111 Parasitic Resistor Temperature Equations.

10 111 TriQuint (TOM) Extensions to Level=3 ..111 Level 7 TOM3 (TriQuint s Own Model III) ..113 Using the TOM3 Model ..113 Model Description ..114DC Equations ..114 Capacitance Equations ..116 Level 8 Materka Model..119 Using the Materka Model ..119DC Model ..119 HSPICE Elements and Device Models Capacitance Model ..120 Noise Model .. Models ..125 Overview of BJT Models ..126 Selecting Models ..126 BJT Control Options ..127 Convergence ..127 BJT Model Statement..127 BJT Basic Model Parameters..128 Bypassing Latent Devices ..129 Parameters ..129 BJT Model Temperature Effects ..137 BJT Device Equivalent Circuits ..143 Scaling ..143 BJT Current Conventions ..144 BJT Equivalent Circuits ..144 BJT Model Equations (NPN and PNP) ..155 Transistor Geometry in Substrate Diodes ..155DC Model Equations ..156 Substrate Current Equations ..157 Base Charge Equations ..158 Variable Base Resistance Equations.