HSPICE Simulation and Analysis User Guide

1 HSPICE Simulation and Analysis User GuideVersion , September 2005iiHSPICE Simulation and Analysis User Notice and Proprietary InformationCopyright 2005 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary information that is the property of Synopsys, Inc. The software and documentation are furnished under a license agreement and may be used or copied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced, transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written permission of Synopsys, Inc., or as expressly provided by the license to Copy DocumentationThe license agreement with Synopsys permits licensee to make copies of the documentation for its internal use only. Each copy shall include all copyrights, trademarks, service marks, and proprietary rights notices, if any. Licensee must assign sequential numbers to all copies.

2 These copies shall contain the following legend on the cover page: This document is duplicated with the permission of Synopsys, Inc., for the exclusive use of _____ and its employees. This is copy number _____. Destination Control StatementAll technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader s responsibility to determine the applicable regulations and to comply with , INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR Trademarks ( )Synopsys, AMPS, Arcadia, C Level Design, C2 HDL, C2V, C2 VHDL, Cadabra, Calaveras Algorithm, CATS, CRITIC, CSim, Design Compiler, DesignPower, DesignWare, EPIC, Formality, HSIM, HSPICE , Hypermodel, iN-Phase, in-Sync, Leda, MAST, Meta, Meta-Software, ModelTools, NanoSim, OpenVera, PathMill, Photolynx, Physical Compiler, PowerMill, PrimeTime, RailMill, RapidScript, Saber, SiVL, SNUG, SolvNet, Superlog, System Compiler, Testify, TetraMAX, TimeMill, TMA, VCS, Vera, and Virtual Stepper are registered trademarks of Synopsys, ( )

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4 Star-SimXT, Star-Time, Star-XP, SWIFT, Taurus, TimeSlice, TimeTracker, Timing Annotator, TopoPlace, TopoRoute, Trace-On-Demand, True- HSPICE , TSUPREM-4, TymeWare, VCS Express, VCSi, Venus, Verification Portal, VFormal, VHDL Compiler, VHDL System Simulator, VirSim, and VMC are trademarks of Synopsys, Marks (SM)MAP-in, SVP Caf , and TAP-in are service marks of Synopsys, is a trademark of the Open SystemC Initiative and is used under and AMBA are registered trademarks of ARM other product or company names may be trademarks of their respective owners. Printed in the Simulation and Analysis User Guide , Simulation and Analysis User This Manual xxiiiInside This Manual..xxiiiThe HSPICE Documentation Set..xxvSearching Across the HSPICE Documentation Set..xxviOther Related Publications ..xxviConventions ..xxviiCustomer Support ..xxviiiAccessing SolvNet xxviiiContacting the Synopsys Technical Support Center ..1 HSPICE Varieties..2 Features ..3 HSPICE Features for Running Higher-Level Simulations.

5 5 Simulation Structure ..6 Experimental Methods Supported by HSPICE ..6 HSPICE Data Flow..7 Simulation Process Overview .. and Simulation ..11 Setting Environment Variables ..11 Setting License Variables ..11 License Queuing ..12 Standard Input Files..13 Design and File Naming Conventions ..13 Output Configuration File ..14 Initialization File ..14ivHSPICE Simulation and Analysis User Operating Point Initial Conditions File)..15 Input Netlist File ..15 Library Input File ..15 Analog Transition Data File ..15 Standard Output Files ..16AC Analysis Results File ..17AC Analysis Measurement Reults File ..17DC Analysis Results File ..18DC Analysis Measurement Results File..18 Digital Output File..18 FFT Analysis Graph Data File ..18 Hardcopy Graph Data File ..18 HBLSP Analysis Extraction Results File ..18 HBLSP Analysis Results File ..19 HBLSP Analysis Print Information File..19 Operating Point Information File..19 Operating Point Node Voltages File ..19 Output Listing File.

6 19 Output Status File ..20 Output Tables ..21 Subcircuit Cross-Listing File..21 Transient Analysis Measurement Results File ..21 Transient Analysis Results File ..21 Starting HSPICE ..22 Redirecting Output ..23 Running an HSPICE Simulation ..24 Interactive Simulation ..26 Examples of Starting HSPICE ..26 Starting HSPICE RF ..28 Improving Simulation Performance with Multithreading ..29 Running HSPICE -MT ..29 Performance Improvement Estimations ..30 Simulating in Client/Server Mode..30 Server..31 Client ..31 Simulating with Stand-alone .MEASURE Calculations ..33 HSPICE Simulation and Analysis User Netlist and Data Entry ..35 Input Netlist File Guidelines ..35 Input Line Format ..36 First Character ..38 Delimiters ..38 Node Identifiers ..39 Instance Names ..39 Hierarchy Paths ..41 Numbers..41 Parameters and Expressions ..42 Input Netlist File Structure ..43 Schematic Netlists ..43 Input Netlist File Composition ..45 Title of Simulation ..46 Comments and Line Continuation.

7 47 Element and Source Statements ..48 Defining Subcircuits ..50 Node Naming Conventions ..50 Using Wildcards on Node Names ..51 Element, Instance, and Subcircuit Naming Conventions ..53 Subcircuit Node Names ..53 Path Names of Subcircuit Nodes ..54 Abbreviated Subcircuit Node Names ..55 Automatic Node Name Generation ..55 Global Node Names..56 Circuit Temperature ..56 Data-Driven Analysis ..56 Library Calls and Definitions ..57 Library Building Rules ..57 Automatic Library Selection ..57 Defining Parameters..58 Predefined Analysis ..58 Measurement Parameters ..59 Altering Design Variables and Subcircuits ..59 Using Multiple .ALTER Blocks ..60 Connecting Nodes ..60 Deleting a Library ..61 Ending a Netlist ..61viHSPICE Simulation and Analysis User Netlists (IF-ELSE)..61 Using Subcircuits ..63 Hierarchical Parameters..64M (Multiply) Parameter ..64S (Scale) Parameter ..65 Using Hierarchical Parameters to Simplify Simulation ..65 Undefined Subcircuit Search ..66 Subcircuit Call Statement Discrete Device Libraries.

8 67 DDL Library Access ..67 Vendor Libraries ..68 Subcircuit Library Structure ..71 Passive Elements..71 Values for Elements ..71 Resistor Elements in a HSPICE or HSPICE RF Netlist ..72 Linear Resistors ..74 Behavioral Resistors in HSPICE or HSPICE RF ..75 Frequency-Dependent Resistors ..76 Skin Effect Resistors ..77 Capacitors ..77 Linear Capacitors ..80 Frequency-Dependent Capacitors ..81 Behavioral Capacitors in HSPICE or HSPICE RF ..83DC Block Capacitors ..83 Charge-Conserved Capacitors..84 Inductors ..85 Mutual Inductors..88 Ideal Transformer ..90 Linear Inductors ..92 Frequency-Dependent Inductors ..93AC Choke Inductors ..94 Active Elements ..95 Diode Element ..95 Bipolar Junction Transistor (BJT) Element ..97 JFETs and MESFETs ..100 MOSFETs ..102 Transmission Lines ..105W Element ..105 HSPICE Simulation and Analysis User Element Statement ..106 Lossless (T Element) ..110 Ideal Transmission Line ..112 Lossy (U Element) ..114 Frequency-Dependent Multi-Terminal S Element.

9 115 Frequency Table Model ..121 Group Delay Handler in Time Domain Analysis ..121 Pre-Conditioning S Parameters ..122 IBIS Buffers .. and Stimuli ..125 Independent Source Elements..125 Source Element Conventions..126 Independent Source Element..126DC Sources ..129AC Sources ..130 Transient Sources ..130 Mixed Sources ..130 Port Element ..131 Independent Source Functions ..135 Pulse Source Function ..135 Sinusoidal Source Function ..139 Exponential Source Function ..142 Piecewise Linear (PWL) Source Function ..145 General Form ..145 MSINC and ASPEC Form ..145 Data-Driven Piecewise Linear Source ..147 Single-Frequency FM Source Function ..149 Amplitude Modulation Source Function ..151 Pattern Source Function ..153 Nested-Structure Pattern Source ..156 Pattern-Command Driven Pattern Source ..157 Pseudo Random-Bit Generator Source (PRBS Function) ..158 Linear Feedback Shift Register ..159 Conventions for Feedback Tap Specification ..159 PRBS Syntax ..160 Voltage and Current Controlled Elements.

10 162 Polynomial Functions ..164viiiHSPICE Simulation and Analysis User Function..164 Two-Dimensional Function ..165 Three-Dimensional Function ..166 Piecewise Linear Function ..167 Power Sources..168 Independent Sources ..168 Outputs..171 Controlled Sources..171 Voltage-Dependent Voltage Sources E Elements ..171 Voltage-Controlled Voltage Source (VCVS) ..172 Linear ..172 Polynomial (POLY) ..172 Piecewise Linear (PWL) ..172 Multi-Input Gates ..172 Delay Element ..172 Laplace Transform ..173 Pole-Zero Function ..174 Frequency Response Table ..175 Behavioral Voltage Source ..176 Ideal Op-Amp ..176 Ideal Transformer ..176E Element Examples ..179 Ideal OpAmp ..179 Voltage Summer ..180 Polynomial Function ..180 Zero-Delay Inverter Gate ..181 Ideal Transformer ..181 Voltage-Controlled Oscillator (VCO)..181 Using the E Element for AC Analysis ..181 Current-Dependent Current Sources F Elements ..182 Current-Controlled Current Source (CCCS) Syntax..182 Linear ..182 Polynomial (POLY).