Ilango Ganga, Intel - IEEE 802

1 01/23/2008 IEEE interim meeting, Portland, OR140/ 100g Architecture & Interfaces proposalIlango Ganga, IntelJan 23, 2008 01/23/2008 IEEE interim meeting, Portland, OR2 Agenda Proposed 40/ 100g architecture Inter-sublayer interfaces Summary01/23/2008 IEEE interim meeting, Portland, OR3 Proposed 40 GbE architectureLLC (LOGICAL LINK CONTROL) OR OTHER MAC CLIENTMAC CONTROL (OPTIONAL)MAC MEDIA ACCESS CONTROLRECONCILLIATIONHIGHER LAYERSPCSFECPMAPMDANMEDIUMMDIMEDIUMMDIME DIUMMDI 40 GBASE-KR4 PCSFEC?PMAPMDPCSFEC?PMAPMD 40 GBASE-CR4 40 GBASE-?R4 Copper (short reach)Fiber OM3 MMFXLGMIIB ackplane Proposal based on discussions in HSSG 4 lanes of 10G R PCS (64B/66B code) Proposal for MAC/PHY interface xMII for intra-chip connectivity xAUI for inter-chip connectivityXLGXSXLGXSXLAUIXLGMIIXLGMIIX LGXSXLGXSXLAUIXLGMIIXLGMIIXLGXSXLGXSXLAU IXLGMII01/23/2008 IEEE interim meeting, Portland, OR4 Proposed 40 GbE backplane architectureXGMIIGMIIXGMIIPMDPMA8B/10B PCSR econciliationPMDPMA8B/10B PCSPMDPMA64B/66B PCSMDIFECMACXLGMIIPMDPMA64B/66B PCSFECAuto-NegotiationBackplane Medium1000 BASE-KX10 GBASE-KX410 GBASE-KR 40 GBASE-KR4 Optional XLGMII ExtenderLeverage 10 GBASE-KR01/23/2008 IEEE interim meeting, Portland, OR5 Proposed 100 GbE architectureLLC (LOGICAL LINK CONTROL) OR OTHER MAC CLIENTMAC CONTROL (OPTIONAL)

2 MAC MEDIA ACCESS CONTROLRECONCILLIATIONHIGHER LAYERSMEDIUMMDIMEDIUMMDIPCSFEC?PMAPMDPCS FEC?PMAPMD 100 GBASE-??? 100 GBASE-??? Fiber 10Km SMFF iber 40Km SMFMEDIUMMDIPCSFEC?PMAPMD 100 GBASE-??? Fiber 100m OM3 MMFMEDIUMMDIPCSFEC?PMAPMD 100 GBASE-??? Short Reach CopperCGMIICGXSCGXSCAUICGMIICGMIICGXSCGX SCAUICGMIICGMIICGXSCGXSCAUICGMIICGMIIXLG XSXLGXSCAUICGMII01/23/2008 IEEE interim meeting, Portland, OR6 Proposed 40/100 GbE interfacesXLGMII/CGMIIMEDIUMMDIPCSFECPMA PMD 40 GBASE-?R4 or 100 GBASE-???FEC Service Interface (abstract)PMA Service Interface (physical)PMD Service Interface (abstract)XLGXS or CGXSXLGXS or CGXSXLGMII/CGMII(logical)XLAUI/CAUIXLGMI I or CGMII EXTENDERRS, MAC AND HIGHER LAYERS Inter-sublayer interfaces common to 40/ 100g where possible XLGMII or CGMII Logical.

3 Define data, clock, no electricals XLAUI or CAUI Physical, define electricals FEC service interface Abstract PMA Service interface Physical, define electricals PMD Service interface AbstractNote: XL Roman numeral for 40C Roman numeral for 10001/23/2008 IEEE interim meeting, Portland, OR7 Interface solutions needed (1) XLGMII (Forty Gigabit MII) or CGMII (100 Gigabit MII) PCS interface Interface between MAC and PHY layers needed for intra-chip connectivity Need for Compatibility interface Process advancements drive System on Chip (SoC) implementations Example: 90nm, 65nm, 45nm and beyond Multiple vendors develop IP blocks for same SoC, for example MAC and PHY layers from different vendors need to interoperate Logical definition, data width, clock frequency, No electricals XLGMII and CGMII can have same definition, different data width and clock frequency XLGMII or CGMII Extender (XLAUI / CAUI) Interface between MAC and PHY layers needed for inter-chip connectivity Plan for physical instantiation of an interface similar to XAUI for 10 GbE XAUI is widely used as MAC - PHY interface Optimize for power, allows higher integration.

4 Switches, multi-port LAN controllers Physical definition, differential signaling, signaling rate, short reach channel Lane width: 4 lane for XLAUI, and 4 or 10 lane for CAUI; 64B/66B encoding01/23/2008 IEEE interim meeting, Portland, OR8 Interface solutions needed (2) FEC Service interface Abstract interface between PCS and optional FEC sublayer PMA Service interface Optional physical instantiation allows implementations as Module interface 4 lane serial interface for 40G Decide on 10 lanes versus 4 lanes for 100g Define electricals and channel characteristics Short reach channels with minimum one pair of connectors Historically module interface has been standardized outside of IEEE PMD Service interface Abstract definition PMA and PMD may be implemented together in the same module01/23/2008 IEEE interim meeting, Portland.

5 OR9 Summary Build consensus on 40/ 100g high level architecture Architecture to allow scalability and leverage 10G where possible Consider dual or multi-speed system implementations with 10/40/ 100g Define solutions based on architecture MAC/PHY interface XLGMII/CGMII as compatibility interface for intra-chip connectivity XLGMII/CGMII extender - XLAUI/CAUI interface for inter-chip connectivity Optional Physical instantiation of PCS, and PMA/PMD interfaces Define PCS interface and electricals Define PMA interface and electricals for module connectivity Decide on Industry standard versus IEEE standar