Transcription of Ilango Ganga, Intel - IEEE 802
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Ilango Ganga, Intel - IEEE 802
01/23/2008 IEEE interim meeting, Portland, OR140/ 100g Architecture & Interfaces proposalIlango Ganga, IntelJan 23, 2008 01/23/2008 IEEE interim meeting, Portland, OR2 Agenda Proposed 40/ 100g architecture Inter-sublayer interfaces Summary01/23/2008 IEEE interim meeting, Portland, OR3 Proposed 40 GbE architectureLLC (LOGICAL LINK CONTROL) OR OTHER MAC CLIENTMAC CONTROL (OPTIONAL)MAC MEDIA ACCESS CONTROLRECONCILLIATIONHIGHER LAYERSPCSFECPMAPMDANMEDIUMMDIMEDIUMMDIME DIUMMDI 40 GBASE-KR4 PCSFEC?PMAPMDPCSFEC?PMAPMD 40 GBASE-CR4 40 GBASE-?R4 Copper (short reach)Fiber OM3 MMFXLGMIIB ackplane Proposal based on discussions in HSSG 4 lanes of 10G R PCS (64B/66B code) Proposal for MAC/PHY interface xMII for intra-chip connectivity xAUI for inter-chip connectivityXLGXSXLGXSXLAUIXLGMIIXLGMIIX LGXSXLGXSXLAUIXLGMIIXLGMIIXLGXSXLGXSXLAU IXLGMII01/23/2008 IEEE interim meeting, Portland, OR4 Proposed 40 GbE backplane architectureXGMIIGMIIXGMIIPMDPMA8B/10B PCSR econciliationPMDPMA8B/10B PCSPMDPMA64B/66B PCSMDIFECMACXLGMII
01/23/2008 IEEE 802.3ba interim meeting, Portland, OR 1 40/100G Architecture & Interfaces proposal Ilango Ganga, Intel Jan 23, 2008
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