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PAM4 digital receiver performance and feasibility - …
pam4 digital receiver performance and feasibilitypyVasu ParthasarathyJan 2012 Jan and Contributors Howard Frazier, Broadcom Will Bliss, Broadcom Kent Lusted, Intel Rich Mellitz Intel Rich Mellitz, Intel Sanjay Kasturia, Inphi Hamid Rategh, Inphi Adee Ran, Intel Matt Brown, Applied MicroObjectives Explore pam4 performance on channels submitted to .ap as well as recent submissions These channels have generally been accepted as difficult for most line These channels have generally been accepted as difficult for most line codes Evaluate tradeoffs between complexity and performance with a digital ADC based receiver architectureADC based receiver architecture Demonstrate technical feasibility of the architecture for supporting 100 Gbps operation100 GBASE-KR4 digital Transceiver Block DiagramTxdeemphDriverTxPre-coderith blkPMA fFECdde-emphwith block terminationframerencoder TIMING RECOVERY-ePre-coder dd/FECVGAADCFFESLICER+FECCTF decoder/FECDFEeeeSimulation Setup digital receiver Architecture3 t FFE (1 1 i 1 t) ki filt ( 8db bt t Nit) ADC 32 t FFE 2 t 3 tap FFE (1 pre,1 main, 1 post), peaking filter (~8db boost at Nyquist)
PAM4 digital receiver ppyerformance and feasibility Vasu Parthasarathy Jan 2012 www.broadcom.com
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