Initialization Sequence For DDR SDRAM - TU …

1 - Rev. A 1/04 EN1 2003 Micron Technology, Inc. All rights reserved. TN-46-08 Initialization Sequence for DDR SDRAMTECHNICAL NOTEINITIALIZATION Sequence FOR DDR SDRAMI ntroductionSDRAM is a volatile and complex memory is, when the power is removed, all contents andoperating configurations are lost. Each time the mem-ory is powered up, the device requires a defined proce-dure to initialize the internal state machines and toconfigure the various user defined operating technical note concentrates on the flow for theinitialization Sequence and the configurable DDR SDRAMTo ensure device functionality a predefinedsequence must occur at device power-up or in con-junction with a power-on reset. Step 1 Provide power. The device core power (VDD) anddevice I/O power (VDDQ) must be brought up simulta-neously to prevent device latch-up.

2 At all times, VDDQ must be greater than or equal to VIN (DC) not required, both VDD and VDDQ are typi-cally from the same power 2 Apply the reference voltage (VREF), then the termi-nation voltage (VTT). The reference voltage may rampanytime after VDDQ and should always be equal toVDDQ/2. During ramp, it is extremely important thatthe voltage at the device I/O pin does not exceed thatof VDDQ. Typically, the termination resistors will pro-vide an IR drop between the actual VTT levels andinput voltage at the DRAM 3 Assert and hold clock enable (CKE) to a LVCMOS logic LOW level. During the initial power ramp, theCKE input will not recognize SSTL_2 logic levels. ALOW level on CKE will prevent unwanted commandsto be received by the DRAM and will keep the DRAM from driving the I/O 4 Once the system has established reliable devicepower and CKE has been driven LOW, it is safe to applya stable 5 There must be at least 200 s of valid clocks beforeany command may be given to the 6To initialize the internal logic of the DRAM, bringCKE to a SSTL_2 logic HIGH and assert either a NOP orDESELECT on the command bus.

3 Note, at this point,the CKE input transitions from a LVCMOS input to aSSTL_2 input only and will remain an SSTL_2 7 Assert a PRECHARGE ALL 8 Provide NOPs or DESELECT commands for at 9 Using the LMR command, program the extendedmode register. At this point, the DLL must be config-ured (set E0 = 0 to enable the DLL) and the I/O drivestrength (set E1 = 1 for standard drive or E1 = 0 forreduced drive levels). All other bits must be set to 10 Provide NOPs or DESELECT commands for at 11 Using the LMR command, program the mode regis-ter for the desired operating modes. Note, all MR bitsother than M0 through M7 must be set to zero. Thisstep also performs a DLL reset. Anytime a DLL resetoccurs, 200 clock cycles must be provided before anyREAD command may be 12 Provide NOPs or DESELECT commands for at leasttMRD.

4 TN-46-08 Initialization Sequence for DDR SDRAM09005aef80eaf953 Micron Technology, Inc., reserves the right to change products or specifications without - Rev. A 1/04 EN2 2003 Micron Technology, Inc. All rights 13 Issue a PRECHARGE ALL command with A10 set toa logic HIGH level. Step 14 Provide NOPs or DESELECT commands for at 15 Issue an AUTO REFRESH command. Note, as part ofthe Initialization Sequence , there must be two AUTOREFRESH commands issued. The standard flow is toissue one at Step 15 and one at Step 17. Alternately,these may occur anytime after Step 16 Provide NOPs or DESELECT commands for at 17 Issue the second AUTO REFRESH 18 Provide NOPs or DESELECT commands for at 19 Although not required for Micron devices, JEDEC requires an LMR command to clear the DLL bit (set M8= 0). If a LMR command is issued, the same operatingparameters should be set as configured in Step 20 Provide NOPs or DESELECT commands for at 21 The DRAM has been properly initialized and isready for any valid command.

5 Note, 200 clock cyclesare required between the DLL reset at Step 11 and anyREAD 1: Initialization Flow DiagramVDD and VDDQ RampApply VREF and VTTCKE must be LVCMOS LowApply stable CLOCKsBring CKE High with a NOP command (CKE changes to an SSTL_2 input)Wait at least 200usPRECHARGE ALLA ssert NOP or DESELECT for tRP timeConfigure Extended Mode RegisterConfigure Load Mode Register and reset DLLA ssert NOP or DESELECT for tMRD timeAssert NOP or DESELECT for tMRD timePRECHARGE ALLI ssue AUTO REFRESH commandAssert NOP or DESELECT for tRFC timeOptional LMR command to clear DLL bitAssert NOP or DESELECT for tMRD timeDRAM is ready for any valid commandStep12345678910111213141516171819 2021 Assert NOP or DESELECT commands for tRFCI ssue AUTO REFRESH commandAssert NOP or DESELECT for tRP time TN-46-08 Initialization Sequence for DDR SDRAM09005aef80eaf953 Micron Technology, Inc.

6 , reserves the right to change products or specifications without - Rev. A 1/04 EN3 2003 Micron Technology, Inc. All rights of Operating Parameters As part of the Initialization routine the device oper-ating parameters must be set. For standard DDR-1 SDRAM this includes two internal registers, the ModeRegister (MR) and the Extended Mode Register (EMR). The LOAD MODE REGISTER command (LMR) isused to program the mode registers. The LMR com-mand is issued in conjunction with the DRAM bankaddresses (BA1 and BA0), selects either the MR or theEMR. The DRAM row addresses (A13 A0) provide theop-code to be written. The least significant rowaddress corresponds to the least significant bit withinthe mode RegisterThe mode register has seven configurable bits thatmay be dynamically updated to reflect changing sys-tem requirements.

7 They include (M0-M2) which areused to set the burst length, (M3) which is used to setthe burst type, (M4-M6) which define the CAS Latencyand (M8) which is used to perform a DLL reset. Allother bits are reserved for future use and must be set tozero. To address the mode register, set BA1 = 0 andBA0 = 2: Mode RegisterExtended Mode RegisterThe EMR has two configurable bits that usually arenot changed once the device has been initialized. Bit(E0) is used to enable the device DLL and bit (E2)defines the output drive strength. All other bits arereserved for future use and must be set to zero. Topoint to the EMR, set BA1 = 0 and BA0 =1. Figure 3: Extended Mode RegisterOperating Mode Normal OperationNormal Operation/Reset DLLAll other states reserved01-00-00-00-00-00-ValidValid- 01 Burst Type SequentialInterleavedCAS LatencyReservedReserved23 (DDR400 only) LengthCAS Latency BT0A9A7 A6 A5 A4 A3A8A2 A1 A0 Mode Register (Mx)Address Bus9765438210M3M401010101M500110011M6000 01111M6-M0M8M7 Operating ModeA10A12A11BA0BA110111214015 Note:1) BA1 and BA0 must be 0, 0 to select the mode register (vs.

8 The extended mode register). 2) A13 is only utilized on the 1Gb ) A12 is only utilized on 256Mb and larger LengthReserved248 ReservedReservedReservedReservedM0010101 01M100110011M20000111113A1300-M13 Operating Mode ReservedReserved 0 0 Valid 01 DLLE nableDisableDLL10A9A7 A6 A5 A4 A3A8A2 A1 A0 Extended ModeRegister (Ex)Address Bus9765438210E0 01 Drive StrengthNormalReducedE1E2E0E1,Operating ModeA10A11A12BA1 BA01011131415E3E40 0 0 0 0 E6E5E7E8E90 0 E10E110 E12DS0 12A13 Note:1) To access the extended mode register BA1 must equal "0" and BA0 must equal a "1".2) A13 is only utilized on the 1Gb ) A12 is only utilized on 256Mb and larger ) Reduced drive strength is avaliable on x16 devices E13 TN-46-08 Initialization Sequence for DDR SDRAM09005aef80eaf953 Micron Technology, Inc., reserves the right to change products or specifications without - Rev.

9 A 1/04 EN4 2003 Micron Technology, Inc. All rights reserved. 8000 S. Federal Way, Box 6, Boise, ID 83707-0006, Tel: 208-368-3900E-mail: Internet: , Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective 4: Initialization Waveform SequenceSummaryThe correct DRAM Initialization Sequence must befollowed whenever the device is first powered up orany time there is an interruption in device power. Fail-ure to follow documented procedures will jeopardizedevice functionality. The steps in this technical noteprovide a general flow for proper Initialization ; forexact device timing or device voltage levels, refer to theDDR component data sheet(s). For the latest datasheets, please refer to Micron s Web site LEVELDQBank Address(BA0, BA1)200 cycles of CK with CKE high are required before any READ commandLoad ExtendedMode RegisterLoad ModeRegistertMRDtMRDtRPtRFCtRFC5tISPower -up.

10 VDD and CK stableT = 200 sHigh-ZtIHDMDQSHigh-ZAddresses RAA10 RAALL BANKSCKCK#tCHtCLtCKVTTVREFVDDVDDQCOMMAND LMRNOPPRELMRARARACT5tIStIHBA0 = H,BA1 = LtIStIHtIStIHBA0 = L,BA1 = LtIStIH()()()()()()()()CODE CODE tIStIHCODE CODE PREALL BANKStIStIHT0T1Ta0Tb0Tc0Td0Te0Tf0()()DON T CAREBA()()()()()()()()()()()()()()()()() ()()()()()()()()()()()tRP()()()()()()()( )()()()()()()()()()()()()()()()()()()()( )()()()()()()()()()()()()()()()()()()()( )()()()()()()()()()()()()()()()()()()()( )()()()()()()()()()()()()()()()()()()()( )()()()()()()()()()()()()()()()()()()()( )()()()()()()()()()()()()()()()()()()()( )()()()()()()()()()()()()()()()()()()()( )()()()()()()()()()()()()()()()()()()()( )()()()()()()()()()()()()()()()()()()()( )()()()()