Intel® Ethernet Controller I210 Datasheet

1 January 2021 Revision Number: No. 333016-011 Intel Ethernet Controller I210 DatasheetNetworking Division (ND)Features: Small package: 9 x 9 mm PCIe ( GT/s) x1, with Switching Voltage Regulator (iSVR) Integrated Non-Volatile Memory (iNVM) Three single port SKUs: SerDes, Copper, Copper IT Value Part (Intel Ethernet Controller I211) Platform Power Efficiency IEEE Energy Efficient Ethernet (EEE) Proxy: ECMA-393 and Windows* logo for proxy offload Advanced Features: 0 to 70 C commercial temp erature or -40 to 85 C industrial temperature Audio-video bridging IEEE 1588 precision time synchronization IEEE traffic shaper (with software extensions) Jumbo frames Interrupt moderation, VLAN support, IP checksum offload PCIe OBFF (Optimized Buffer Flush/Fill) for improved system power management Four transmit and four receive queues RSS and MSI-X to lower CPU utilization in multi-core systems Advanced cable diagnostics, auto MDI-X ECC error correcting memory in packet buffers Four Software Definable Pins (SDPs) Manageability.

2 NC-SI for greater bandwidth pass through SMBus low-speed serial bus to pass network traffic Flexible firmware architecture with secure Flash update MCTP over SMBus/PCIe OS2 BMC/CEM (optionally enabled via external Flash) PXE and iSCSI boot2No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document (and any related software) is Intel copyrighted material, and your use is governed by the express license under which it is provided to you. Unless the license provides otherwise, you may not use, modify, copy, publish, distribute, disclose or transmit this document (and related materials) without Intel's prior written permission. This document (and related materials) is provided as is, with no express or implied warranties, other than those that are expressly stated in the disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non- infringement , as well as any warranty arising from course of performance, course of dealing, or usage in document contains information on products, services and/or processes in development.

3 All information provided here is subject to change without notice . Contact your Intel representative to obtain the latest forecast, schedule, specifications and products and services described may contain defects or errors which may cause deviations from published of documents which have an order number and are referenced in this document may be obtained by calling 1-800-548-4725 or by visiting and the Intel logo are trademarks of Intel Corporation in the and/or other names and brands may be claimed as the property of others. 2021 Intel History Ethernet Controller I2103 Revision 2021 Added section [ROM-based Firmware (Firmware Authentication)].Updated section [Internal Non-Volatile Memory (iNVM)]. 2020 Updated Section (Programming Interface).Updated the note below Figure 12-27 (Peak Temperature). 2019 Updated Section (Power Supply Specification). 2019 Updated Section (new validated Flash parts).

4 2018 Updated Section [LaunchTime (25)]. 2018 Updated Table 2-1 (Pull-Up/Pull-Down Resistors).Added section (iNVM Structure Version Information).Updated section (Timing Guarantees).Updated section (Port Identification LED Blinking; Word 0x04).Updated section (Flash Parts). 2017 Revised Section: (iNVM Programming Flows). 2017 Revised Sections: (Internal PHY Power-Down State). (MDIO AC Specification). (Oscillator Support). (XOR Testing). 2016 Revised Table 2-1 (changed JTAG_CLK to show a pull down resistor instead of a pull up). Updated intra-document cross references. Revised the description of Section (Synchronized Output Clock on SDP Pins). Revised Section (TimeSync Auxiliary Control Register - TSAUXC (0xB640; RW), bit 4 and bit 7 description). 2015 Revised Section (added image build information). Updated Table 11-11 (tDS and tDH descriptions). Updated Table 11-15 (cload value).

5 Updated Figure (changed pull-up value from to ). Updated Section (Diff to CMR value). Added Section (Maximum Trace Lengths Based on Trace Geometry). Fixed cross references in Section 2015 Removed all references to IEEE Std , IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks, IEEE, 2003. Updated section (Misc Test - Page 6, Register 26). Removed sections through Updated section 12-4 (Oscillator Support). Added section (Designing the I210 as a 10/100 Mb/s Only Device). Updated section (Differential Pair Trace Routing for 10/100/1000 Designs). 2014 Revised section (replaced W25Q16 DWSSIG with W25Q16 DVSSIG). 2014 Replaced figure 2-2. Revised section (iNVM). Revised section (iNVM Structures). Revised section (Internal PHY Back-to-Back SPD). Revised table 8-6 (Register Summary; PQMPRC[0 - 3]). Revised table 11-11 (Flash I/F Timing Parameters).

6 Revised table 11-17 (Specification for External Clock Oscillator). Ethernet Controller I210 Revision 2013 Updated revision 2013 Revised section (Audio/Video Bridging Support). Revised section (Common Firmware Parameters 1 - Offset 0x1; bit 15). Revised section (Receive-Side Scaling (RSS). Revised section (Capture Timestamp Mechanism). Revised section (Flexible Host Filter Table Registers - FHFT (0x9000 + 4*n [n= ]; RW); updated note. Revised section (MAC Specific Control Register 1 - Page 2, Register 16; bits 9:8). Revised table 10-37 (Decision Filter Values). 2013 Updated title page (Platform Power Efficiency description). Revised VPD Area Update Flow description (section ). Revised iNVM description (section ). Added line loopback information (section ). Revised Acquiring Ownership Over a Shared Resource description (section ). Revised Releasing Ownership Over a Shared Resource description (section ).))

7 Revised Dr Disable Mode description (section ). Revised Device Rev ID (section ). Revised Common Firmware Parameters 1 - Offset 0x1 (section ). Updated Compatibility (Word 0x03) bit 11 description (section ). Updated Setup Options PCIe Function 0 (Word 0x30) bit 5 description (section ). Added PXE VLAN Flash settings (Sections through ). Updated Software Semaphore - SWSM (0x5B50; R/W) Removed Firmware Status Register (0x8F0C) entry from Table 8-6. Revised note (changed .. has both F and L flags off to on (section ). Revised Specification for XTAL1 (In); table Revised Third-Party Magnetics Manufacturers table (section ). Added Power Delivery Solutions (section ). 2012 Revised table - Absolute Maximum Ratings Revised section - Third-Party Magnetics Manufacturers. Revised table - Absolute Maximum Case Temperature. Revised table - Thermal Simulation Results for Various Environmental 2012 The following sections were revised: Introduction.)

8 Interconnects. Flash Map. Inline Functions. Programming Interface. PCIe Programming Interface. Electrical/Mechanical Specification. Design Considerations. Diagnostics Added new section - Thermal 2012 Initial Release (Intel Public).Introduction Ethernet Controller Intel Ethernet Controller I210 ( I210 ) is a single port, compact, low power component that supports GbE designs. The I210 offers a fully-integrated GbE Media Access Control (MAC), Physical Layer (PHY) port and a SGMII/SerDes port that can be connected to an external PHY. The I210 supports PCI Express* [PCIe ( )].The I210 enables 1000 BASE-T implementations using an integrated PHY. It can be used for server system configurations such as rack mounted or pedestal servers, in an add-on NIC or LAN on Motherboard (LOM) design. Another possible system configuration is for blade servers a s a LOM or mezzanine card.

9 It can also be used in embedded applications such as switch add-on cards and network document provides the external architecture (including device operation, pin descriptions, register definitions, etc.) for the I210. This document is a reference for software device driver developers, board designers, test engineers, and others who may need specific technical or programming and AcronymsTable DefinitionMeaning1000 BASE-BX1000 BASE-BX is the PICMG electrical specification for transmitting 1 Gb/s Ethernet or 1 Gb/s fibre channel encoded data over the is the electrical specification for transmitting1 Gb/s Ethernet over the over specialty shielded 150 balanced copper jumper cable assemblies as specified in IEEE Clause is the specification for 1 Gb/s Ethernet over category 5e twisted pair cables as defined in IEEE clause Event Input/Output System. BMCB aseboard Management Controller - often used interchangeably with Manageability Controller (MC).

10 BT Bit Cyclic redundancy checkDCAD irect Cache Device OffEthernet Controller I210 Introduction6 DFTD esign for Descriptor Management Task Force standard word (4 bytes).EEEE nergy Efficient Ethernet - standardEEPROME lectrically Erasable Programmable Memory. A non-volatile memory located on the LAN Controller that is directly accessible from the End of Flow Check (FW)Embedded code on the LAN Controller that is responsible for the implementation of the NC-SI protocol and pass through InterfaceRAM on the LAN Controller that is shared between the firmware and the host. RAM is used to pass commands from the host to firmware and responses from the firmware to the - Performance Processor Packet Platform Management Interface specificationLAN (auxiliary Power-Up)The event of connecting the LAN Controller to a power source (occurs even before system power-up).LLDPLink Layer Discovery Protocol defined in used by (EEE) for system wake time on Power Idle - Low power state of Ethernet link as defined in Send Tolerance Reporting (PCIe protocol)iSVRI ntegrated Switching Voltage RegulatorMACM edia Access ControllerMCTPDMTF Management Component Transport Protocol (MCTP) transport protocol to allow communication between a management Controller and controlled device over various Data Input/Output Interface over MDC/MDIO Inter Frame Spacing/Minimum Inter Packet Memory Segment amount of data, in a packet (without headers) that can be transmitted.