INTEL 80386 PROGRAMMER'S REFERENCE MANUAL 1986

1 INTEL 80386 PROGRAMMER'S REFERENCE MANUAL 1986 Page 1 of 421 INTEL 80386 PROGRAMMER'S REFERENCE MANUAL1986 INTEL Corporation makes no warranty for the use of its products andassumes no responsibility for any errors which may appear in this documentnor does it make a commitment to update the information contained retains the right to make changes to these specifications at anytime, without your local sales office to obtain the latest specifications beforeplacing your following are trademarks of INTEL Corporation and may only be used toidentify INTEL Products:Above, BITBUS, COMM puter, CREDIT, Data Pipeline, FASTPATH, Genius, i, ,ICE, iCEL, iCS, iDBP, iDIS, I ICE, iLBX, im, iMDDX, iMMX, Inboard,Insite, INTEL , INTEL , intelBOS, INTEL Certified, Intelevision,inteligent Identifier, inteligent Programming, Intellec, Intellink,iOSP, iPDS, iPSC, iRMK, iRMX, iSBC, iSBX, iSDM, iSXM, KEPROM, LibraryManager, MAPNET, MCS, Megachassis, MICROMAINFRAME, MULTIBUS, MULTICHANNEL,MULTIMODULE, MultiSERVER, ONCE, OpenNET, OTP, PC BUBBLE, Plug-A-Bubble,PROMPT, Promware, QUEST, QueX, Quick-Pulse Programming, Ripplemode, RMX/80,RUPI, Seamless, SLD, SugarCube, SupportNET, UPI, and VLSiCEL, and thecombination of ICE, iCS, iRMX, iSBC, iSBX, iSXM, MCS, or UPI and a numericalsuffix, is an ordering code only and is not used as a product name ortrademark.

2 MDS(R) is a registered trademark of Mohawk Data copies of this MANUAL or other INTEL literature may be obtainedfrom: INTEL CorporationLiterature DistributionMail Stop SC6-593065 Bowers AvenueSanta Clara, CA 95051 INTEL CORPORATION 1987 CG-5/26/87 Edited 2001-02-01 by 80386 PROGRAMMER'S REFERENCE MANUAL 1986 Page 2 of 421 customer Support customer Support is INTEL 's complete support service that provides Intelcustomers with hardware support, software support, customer training , andconsulting services. For more information contact your local sales a customer purchases any system hardware or software product,service and support become major factors in determining whether thatproduct will continue to meet a customer 's expectations. Such supportrequires an international support organization and a breadth of programsto meet a variety of customer needs.

3 As you might expect, INTEL 's customersupport is quite extensive. It includes factory repair services andworldwide field service offices providing hardware repair services,software support services, customer training classes, and Support ServicesIntel is committed to providing an international service support packagethrough a wide variety of service offerings available from INTEL Support ServicesIntel's software support consists of two levels of contracts. Standardsupport includes TIPS (Technical Information Phone Service), updates andsubscription service (product-specific troubleshooting guides and COMMENTSM agazine). Basic support includes updates and the subscription are sold in environments which represent product groupings( , iRMX environment).Consulting ServicesIntel provides field systems engineering services for any phase of yourdevelopment or support effort. You can use our systems engineers in avariety of ways ranging from assistance in using a new product, developingan application, personalizing training , and customizing or tailoring anIntel product to providing technical and management consulting.

4 SystemsEngineers are well versed in technical areas such as microcommunications,real-time applications, embedded microcontrollers, and network know your application needs; we know our products. Working together wecan help you get a successful product to market in the least possible TrainingIntel offers a wide range of instructional programs covering variousaspects of system design and implementation. In just three to ten days alimited number of individuals learn more in a single workshop than inweeks of self-study. For optimum convenience, workshops are scheduledregularly at training Centers woridwide or we can take our workshops toyou for on-site instruction. Covering a wide variety of topics, INTEL 'smajor course categories include: architecture and assembly language,programming and operating systems, bitbus and LAN 80386 PROGRAMMER'S REFERENCE MANUAL 1986 Page 3 of 421 training Center LocationsTo obtain a complete catalog of our workshops, call the nearest TrainingCenter in your (617) 692-1000 Chicago (312) 310-5700 San Francisco (415) 940-7800 Washington (301) 474-2878 Isreal (972) 349-491-099 Tokyo 03-437-6611 Osaka (Call Tokyo) 03-437-6611 Toronto, Canada (416) 675-2105 London (0793) 696-000 Munich (089) 5389-1 Paris (01) 687-22-21 Stockholm (468) 734-01-00 Milan 39-2-82-44-071 Benelux (Rotterdam) (10) 21-23-77 Copenhagen (1)

5 198-033 Hong Kong 5-215311-7 INTEL 80386 PROGRAMMER'S REFERENCE MANUAL 1986 Page 4 of 421 Table of ContentsCUSTOMER SUPPORT .. 2 CHAPTER 1 INTRODUCTION TO THE 80386 .. ORGANIZATION OF THIS Part I Applications Programming .. Part II Systems Programming .. Part III Compatibility .. Part IV Instruction Appendices .. RELATED NOTATIONAL Data-Structure Formats .. Undefined Bits and Software Instruction Operands .. Hexadecimal Numbers .. Sub- and 21 CHAPTER 2 BASIC PROGRAMMING MEMORY ORGANIZATION AND The "Flat" Model .. The Segmented Model .. DATA General Segment Registers .. Stack Implementation .. Flags Register .. Status Flags .. Control Instruction Pointer .. INSTRUCTION OPERAND Immediate Operands .. Register Operands .. Memory Operands .. Segment Selection .. Effective-Address Computation.

6 INTERRUPTS AND 42 CHAPTER 3 APPLICATIONS INSTRUCTION SET .. DATA MOVEMENT General-Purpose Data Movement Instructions .. Stack Manipulation Instructions .. Type Conversion Instructions .. BINARY ARITHMETIC Addition and Subtraction Instructions .. Comparison and Sign Change Instruction .. Multiplication Division Instructions .. DECIMAL ARITHMETIC Packed BCD Adjustment Instructions .. Unpacked BCD Adjustment LOGICAL 80386 PROGRAMMER'S REFERENCE MANUAL 1986 Page 5 of Boolean Operation Instructions .. Bit Test and Modify Instructions .. Bit Scan Instructions .. Shift and Rotate Shift Instructions .. Double-Shift Instructions .. Rotate Fast "BIT BLT" Using Double Shift Fast Bit-String Insert and Extract .. Byte-Set-On-Condition Test Instruction .. CONTROL TRANSFER Unconditional Transfer Jump Instruction .. Call Instruction.

7 Return and Return-From-Interrupt Instruction .. Conditional Transfer Conditional Jump Loop Executing a Loop or Repeat Zero Times .. Software-Generated Interrupts .. STRING AND CHARACTER TRANSLATION Repeat Prefixes .. Indexing and Direction Flag Control .. String INSTRUCTIONS FOR BLOCK-STRUCTURED FLAG CONTROL Carry and Direction Flag Control Instructions .. Flag Transfer Instructions .. COPROCESSOR INTERFACE SEGMENT REGISTER Segment-Register Transfer Far Control Transfer Instructions .. Data Pointer MISCELLANEOUS Address Calculation Instruction .. No-Operation Translate 84 CHAPTER 4 SYSTEMS ARCHITECTURE .. SYSTEMS Systems Memory-Management Registers .. Control Registers .. Debug Test Registers .. SYSTEMS 5 MEMORY MANAGEMENT .. SEGMENT Descriptor Segment Registers .. PAGE Page Linear Address.

8 98 INTEL 80386 PROGRAMMER'S REFERENCE MANUAL 1986 Page 6 of Page Page-Table Entries .. Page Frame Address .. Present Bit .. Accessed and Dirty Bits .. Read/Write and User/Supervisor Page Translation COMBINING SEGMENT AND PAGE "Flat" Segments Spanning Several Pages Spanning Several Non-Aligned Page and Segment Boundaries .. Aligned Page and Segment Boundaries .. Page-Table per Segment .. 104 CHAPTER 6 PROTECTION .. WHY PROTECTION? .. OVERVIEW OF 80386 PROTECTION SEGMENT-LEVEL Descriptors Store Protection Parameters .. Type Checking .. Limit Privilege Levels .. Restricting Access to Data .. Accessing Data in Code Segments .. Restricting Control Transfers .. Gate Descriptors Guard Procedure Entry Points .. Stack Switching .. Returning from a Procedure .. Some Instructions are Reserved for Operating System .. Privileged Sensitive Instructions for Pointer Validation.

9 Descriptor Validation .. Pointer Integrity and PAGE-LEVEL Page-Table Entries Hold Protection Parameters .. Restricting Addressable Domain .. Type Checking .. Combining Protection of Both Levels of Page Tables .. Overrides to Page Protection .. COMBINING PAGE AND SEGMENT 128 CHAPTER 7 MULTITASKING .. TASK STATE TSS TASK TASK GATE TASK TASK Busy Bit Prevents Loops .. Modifying Task Linkages .. TASK ADDRESS Task Linear-to-Physical Space Mapping .. Task Logical Address Space .. 143 CHAPTER 8 INPUT/OUTPUT .. 145 INTEL 80386 PROGRAMMER'S REFERENCE MANUAL 1986 Page 7 of I/O I/O Address Memory-Mapped I/O Register I/O Instructions .. Block I/O Instructions .. PROTECTION AND I/O .. I/O Privilege Level .. I/O Permission Bit Map .. 149 CHAPTER 9 EXCEPTIONS AND INTERRUPTS .. IDENTIFYING ENABLING AND DISABLING NMI Masks Further NMIs.

10 IF Masks INTR .. RF Masks Debug MOV or POP to SS Masks Some Interrupts and PRIORITY AMONG SIMULTANEOUS INTERRUPTS AND INTERRUPT DESCRIPTOR IDT INTERRUPT TASKS AND INTERRUPT Interrupt Stack of Interrupt Returning from an Interrupt Flags Usage by Interrupt Procedure .. Protection in Interrupt Procedures .. Interrupt Tasks .. ERROR EXCEPTION Interrupt 0 Divide Interrupt 1 Debug Exceptions .. Interrupt 3 Interrupt 4 Interrupt 5 Bounds Interrupt 6 Invalid Interrupt 7 Coprocessor Not Available .. Interrupt 8 Double Fault .. Interrupt 9 Coprocessor Segment Overrun .. Interrupt 10 Invalid TSS .. Interrupt 11 Segment Not Present .. Interrupt 12 Stack Exception .. Interrupt 13 General Protection Exception .. Interrupt 14 Page Page Fault During Task Switch .. Page Fault with Inconsistent Stack Interrupt 16 Coprocessor Error.