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Interconnections: Silicides - Stanford University

EE 311 Prof SaraswatInterconnections: Silicides1. Source/Drain JunctionssourceRchSilicideRcRsdrainRdRd Rs metalXjPoly-SiR (total) = Rch + RparasiticRparasitic = Rextension + RextrinsicRextension = Rd + Rs Rextrinsic = Rd + Rs + 2Rc2. MOS Gate ElectrodeAs channel length is scaled, gate resistance increases. Gate electrode is also used asan interconnect layer in many applications. As channel length is scaled, gate resistanceincreasesEE 311 Prof Saraswat3. Local InterconnectTo minimize parasitic resistance we use silicide for:1. Polycide gate (silicide on polysilicon)2.

Stress after deposition Stres after anneal Etch rate variation due to stress Electrical resistivity ρ, stress Δσdep after deposition, stress change Δσsint during sintering and etch rate Retch in CF4 of evaporated TaSi2 films as a function of increasing O2 partial pressure in the residual gas.

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Transcription of Interconnections: Silicides - Stanford University

1 EE 311 Prof SaraswatInterconnections: Silicides1. Source/Drain JunctionssourceRchSilicideRcRsdrainRdRd Rs metalXjPoly-SiR (total) = Rch + RparasiticRparasitic = Rextension + RextrinsicRextension = Rd + Rs Rextrinsic = Rd + Rs + 2Rc2. MOS Gate ElectrodeAs channel length is scaled, gate resistance increases. Gate electrode is also used asan interconnect layer in many applications. As channel length is scaled, gate resistanceincreasesEE 311 Prof Saraswat3. Local InterconnectTo minimize parasitic resistance we use silicide for:1. Polycide gate (silicide on polysilicon)2.

2 Salicide (self aligned silicide) on source-drain3. Local interconnection between devices, , between source/drain diffusion ofone device to gate of another in a SRAM use Silicides ? Low resistance Good process compatibility with Si, , ability to withstand high temperatures,oxidizing ambients, various chemical cleans used during processing. Little or no electromigration Easy to dry etch Good contacts to other these are many problems in integrating Silicides in an IC as we will see later in of silicidesPreferred Silicides for the applications outlined earlier are WSi2,TiSi2, NiSi and CoSi2because of their overall excellent 311 Prof SaraswatSilicideThin filmresistivity( cm)Sinteringtemp( C)Stable onSi up to( C)Reactionwith Al at( C)nm of Siconsumedper nm ofmetalnm ofresultingsilicideper nm ofmetalBarrierheight ton-Si (eV)PtSi28-35250-400~ (C54)13-16700-900~ (C49)

3 ~ ~ ~ ~ ~ ~ Phase DiagramsTernary Phase Diagrams are good indicators of stability. Existance of a tie line indicatesthat the system is stable and a reaction will not take 311 Prof SaraswatSilicide Formation Techniques1. Metal deposition on Si and formation by thermal heating, laser irradiation or Ionbeam mixing. Sensitive to interface cleanliness and heavy doping Selective silicidation on Si possible Widely used for Silicides of Pt, Pd, Co, TiMetalSiEnergy, , heat,laser or IonsSisilicideUnreacted metalSalicide (self-aligned silicide) processSimultaneous silicidation of polysilicon gate, source and drain regions.

4 TiSi2 isextensively used for this process. NiSi and CoSi2 are beginning to be 311 Prof Saraswat2. Co-evaporation (E-gun) of metal and Si Poor process control Poor step coverage Good tool for research but not used in manufacturingMetal3. Sputtering from a composite target Possibility of high level of contaminants (C,O, Na, Ar) Poor step coverage Used for MoSi2 and WSi2 AnodeEE 311 Prof Saraswat4. Cosputtering from two targets of metal and Si Poor step coverage Questionable process control Good tool for research but not used in manufacturingAnodeMetal target5.

5 CVD Good process control for manufacturability Clean microcrystalline films with excellent step coverage Available for only WSi2EE 311 Prof SaraswatEffect of Thermal Processing on Silicide propertiesIn all the silicide formation schemes detailed above, it is usually necessary to subject thesilicide to further thermal processing, either to form the silicide or enhance the grain size. Inparticular, for CVD and deposited Silicides (as opposed to thermally formed Silicides ), grainsize can be enhanced substantially by depositedat 400 C500 C600 C800 CTEM of WSi2 films as deposited by CVD and after annealingRef: K.

6 C. Saraswat, et al., ``Properties of Low Pressure CVD Tungsten Silicide for MOS VLSI Interconnections,''IEEE Transaction Electron Dev., November, example is for CVD WSi2 but is applicable to other Silicides . As deposited films are amorphous or microcrystalline Upon annealing grains grow Higher temperature and longer time give bigger grains Possible phase changeEffect of Annealing on Resistivity As deposited films have high resistivity because they are amorphous or microcrystalline andtherefore carrier mobility is low Upon annealing grains grow and therefore resistivity decreases Higher temperature and longer time give bigger grains and thus lower resistivity correlation with grain growthEE 311 Prof SaraswatResistivity of WSi2 films as

7 Deposited by CVD and after annealingRef: Ref: K. C. Saraswat, et al., ``Properties of Low Pressure CVD Tungsten Silicide for MOS VLSII nterconnections,'' IEEE Transaction Electron Dev., November, of MoSi2, TaSi2 and TiSi2 films as deposited and after annealing. (Ref: Chow,IEEE Trans. Electron. Dev., 1983).EE 311 Prof SaraswatPhysical stress in SilicidesGrain growthCrystal structure changeHeatingCoolingAnnealing may result in substantial stress in the silicide. In addition, there may also be internalstress in the silicide due to the deposition conditions.

8 Since Silicides are typically close tojunctions, and mechanical stress has been found to alter electrical properties of devices, anexamination of this issue is important. stress may be caused by: Internal stress controlledby deposition parameters Difference in thermal expansion rates of Si and silicide Contaminants in silicide Structure and composition of the silicide filmRef: Geipel, et al., IEEE TED.,Aug., 1984. stress in polycide gates can cause gate shorts, cracks, lifting Need a buffer layer of poly-Si to maintain reliabilityEE 311 Prof SaraswatStress can be minimized by making Si rich silicide filmsStress can be generated due to structural changesEE 311 Prof SaraswatEffect of ContaminantsContamination severely changes the properties of Silicides .

9 An effect of oxygencontamination on the properties of TaSi2 films is shown after depositionStres after annealEtch rate variation due to stressElectrical resistivity , stress dep after deposition, stress change sint during sintering andetch rate Retch in CF4 of evaporated TaSi2 films as a function of increasing O2 partial pressure inthe residual gas. All values are normalized to those obtained without additional O2, markedwith a suffix 0 .EE 311 Prof SaraswatThermal Oxidation of SilicidesDuring fabrication the Silicides are exposed to thermal oxidation.

10 It is very importantthay be able to withstand oxidation steps without deterioration in their 311 Prof SaraswatRef: Lie, Tiller and K. C. Saraswat, ``Thermal Oxidation of Silicides ,'' Journal of Applied Physics, (7), October, 1984., pp. 2127--2132. All Silicides show similar oxidation rates Silicides oxidize faster tha SiOxidation Rate ConstantsThe mechanism of oxidation can be easily understood using Deal-Grove type oxidationmodel commonly used for Si: X02B+X0BA=t+ By fitting the oxidation data to the Deal-Grove equation the linear and parabolic rateconstants, B/A and B, respectively, can be 311 Prof SaraswatRef: Lie, Tiller and K.


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