IO-Link Interface and System Specification

1 IO-Link Test Specification Related to IO-Link Interface and System Specification Version July 2014. Order No: IO-Link Test Specification Version _____. File name: This Specification has been prepared by the IO-Link test team and released by the IO-Link community as final version. It covers all Change Requests up to CR-ID161. Any comments, proposals, requests on this document are appreciated. Please use the database for your entries and provide name and email address. Please be aware, that change requests concluded by the IO-Link core team and approved by the IO-Link consortium are mandatory for the performance of the tests. Login: IOL-Test-V112. Password: Report Important notes: NOTE 1 The IO-Link Consortium Rules shall be observed prior to the development and marketing of IO-Link products.

2 The document can be downloaded from the portal. NOTE 2 Any IO-Link device shall provide an associated IODD file. Easy access to the file and potential updates shall be possible. It is the responsibility of the IO-Link Device manufacturer to test the IODD file with the help of the IODD-Checker tool available per download from NOTE 3 Any IO-Link Master or Device shall provide an associated manufacturer declaration on the conformity of the device with the " IO-Link Interface and System " Specification (IEC 61131-9). The manufacturer declaration is available for download from Disclaimer: The attention of adopters is directed to the possibility that compliance with or adoption of IO-Link Consortium specifications may require use of an invention covered by patent rights.

3 The IO-Link Consortium shall not be responsible for identifying patents for which a license may be required by any IO-Link Consortium Specification , or for conducting legal inquiries into the legal validity or scope of those patents that are brought to its attention. IO- link Consortium specifications are prospective and advisory only. Prospective users are responsible for protecting themselves against liability for infringement of patents. The information contained in this document is subject to change without notice. The material in this document details an IO-Link Consortium Specification in accordance with the license and notices set forth on this page.

4 This document does not represent a commitment to implement any portion of this Specification in any company's products. WHILE THE INFORMATION IN THIS PUBLICATION IS BELIEVED TO BE ACCURATE, THE IO- link CONSORTIUM MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS. MATERIAL INCLUDING, BUT NOT LIMITED TO ANY WARRANTY OF TITLE OR OWNERSHIP, IMPLIED. WARRANTY OF MERCHANTABILITY OR WARRANTY OF FITNESS FOR PARTICULAR PURPOSE OR USE. In no event shall the IO-Link Consortium be liable for errors contained herein or for indirect, incidental, special, consequential, reliance or cover damages, including loss of profits, revenue, data or use, incurred by any user or any third party.

5 Compliance with this Specification does not absolve manufacturers of IO-Link equipment, from the requirements of safety and regulatory agencies (T V, BIA, UL, CSA, etc.). is registered trade mark. The use is restricted for members of the IO-Link Community. More detailed terms for the use can be found in the IO-Link Community Rules on Conventions: In this Specification the following key words (in bold text) will be used: may: indicates flexibility of choice with no implied preference. should: indicates flexibility of choice with a strongly preferred implementation. shall: indicates a mandatory requirement. Designers shall implement such mandatory requirements to ensure interoperability and to claim conformity with this Specification .

6 Publisher: IO-Link Community Haid-und-Neu-Str. 7. 76131 Karlsruhe Germany Phone: +49 721 / 96 58 590. Fax: +49 721 / 96 58 589. E-mail: Web site: No part of this publication may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying and microfilm, without permission in writing from the publisher. _____. Copyright IO-Link Community 2014 - All Rights Reserved Page 2 of 397. Test Specification IO-Link 3 Version CONTENTS. 0 Introduction .. 21. General .. 21. Patent declaration .. 21. 1 Scope .. 23. 2 Normative references .. 23. 3 Terms, definitions, symbols, abbreviated terms and conventions .. 23. Terms and definitions.

7 23. Symbols and abbreviated 27. Conventions .. 29. Test case template .. 29. Names of variables .. 30. Memory and transmission octet order .. 31. Behavioral descriptions .. 31. TM. 4 Test strategy for SDCI ( IO-Link ) Master and Devices .. 31. Purpose of this Specification .. 31. Structure of this document .. 31. Conformity classes .. 32. Legacy Devices ( ) .. 32. Devices without ISDU .. 32. Devices with ISDU .. 32. Legacy Master .. 32. Master .. 32. Test of Devices .. 32. Test of SDCI Masters .. 37. 5 Physical Layer (PL) tests .. 41. General .. 41. Static parameters of the Master Interface .. 42. DC supply current capability of Master L+ port .. 42. Power-On supply current capability of Master L+ port.

8 43. Load current at Master C/Q port .. 44. High-side residual voltage at Master C/Q port .. 45. Low-side residual voltage at Master C/Q port .. 46. High-level input threshold voltage at Master C/Q port .. 47. Low-level input threshold voltage at Master C/Q port .. 48. Input hysteresis voltage at Master C/Q port .. 49. High-side peak current capability at Master C/Q port .. 50. Low-side peak current capability at Master C/Q port .. 51. Permissible voltage range at Master C/Q port .. 52. Static parameters of the Device Interface .. 53. Power supply current consumption of the Device .. 53. Power-on behavior of the Device .. 54. High-side residual voltage at Device C/Q port.

9 55. Low-side residual voltage at Device C/Q port .. 56. Pull-down or residual current at C/Q port .. 57. High-level input threshold voltage at Device C/Q port .. 58. Version 4 Test Specification IO-Link Low-level input threshold voltage at Device C/Q port .. 59. Input hysteresis voltage at Device C/Q port .. 60. High-side DC driver limit at Device C/Q port .. 61. Low-side DC driver limit at Device C/Q port .. 62. Permissible voltage range at Device C/Q port .. 63. Wake-Up generation of the Master Interface .. 64. Wake-Up current pulse high .. 64. Wake-Up pulse duration high .. 65. Wake-Up current pulse low .. 66. Wake-Up pulse duration low .. 67. Wake-Up detection of the Device Interface .

10 68. Wake-Up pulse detection high .. 68. Wake-Up pulse detection 69. Wake-Up receive enable delay (C/Q high) .. 70. Wake-Up receive enable delay (C/Q low) .. 71. SDCI readiness delay .. 72. Time to return to SIO after failed wake-up .. 73. Time to Fallback after Master command .. 74. Dynamic parameters of the Master and Device Interface .. 75. Bit eye-diagram with maximum load (Master).. 75. Bit eye-diagram with maximum load (Device).. 76. Bit eye-diagram with minimum load (Master) .. 77. Bit eye-diagram with minimum load (Device) .. 78. UART frame eye-diagram with maximum load (Master) .. 79. UART frame eye-diagram with maximum load (Device) .. 80. UART frame eye-diagram with minimum load (Master).