IRF520 9.2A, 100V, 0.270 Ohm, N-Channel Power MOSFET

1 2002 Fairchild Semiconductor CorporationIRF520 Rev. B IRF520 , 100V, Ohm, N-Channel Power MOSFET This N-Channel enhancement mode silicon gate Power field effect transistor is an advanced Power MOSFET designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these Power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high Power bipolar switching transistors requiring high speed and low gate drive Power . These types can be operated directly from integrated developmental type TA09594. Features , 100V r DS(ON) = SOA is Power Dissipation Limited Single Pulse Avalanche Energy Rated Nanosecond Switching Speeds Linear Transfer Characteristics High Input Impedance Related Literature- TB334 Guidelines for Soldering Surface Mount Components to PC Boards Symbol Packaging JEDEC TO-220AB Ordering Information PART NUMBERPACKAGEBRAND IRF520TO-220 ABIRF520 NOTE: When ordering, use the entire part (FLANGE)DRAINGATE Data SheetJanuary 2002 2002 Fairchild Semiconductor CorporationIRF520 Rev.

2 B Absolute Maximum Ratings T C = 25 o C, Unless Otherwise Specified IRF520 UNITS Drain to Source Breakdown Voltage (Note 1) ..V DS 100 VDrain to Gate Voltage (R GS = 20k ) (Note 1) .. V DGR 100 VContinuous Drain Current .. I D T C = 100 o C .. I D Drain Current (Note 3) .. I DM 37 AGate to Source Voltage ..V GS 20 VMaximum Power Dissipation ..P D 60 WDissipation Derating Factor .. o CSingle Pulse Avalanche Energy Rating (Note 4) ..E AS 36mJOperating and Storage Temperature .. T J, T STG -55 to 175 o CMaximum Temperature for SolderingLeads at ( ) from Case for 10s .. T L Package Body for 10s, See Techbrief 334 .. T pkg 300260 o C o C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of thedevice at these or any other conditions above those indicated in the operational sections of this specification is not implied.

3 NOTE:1. T J = 25 o C to 150 o C. Electrical Specifications T C = 25 o C, Unless Otherwise Specified PARAMETERSYMBOLTEST CONDITIONSMINTYPMAXUNITS Drain to Source Breakdown VoltageBV DSS I D = 250 A, V GS = 0V (Figure 10)100--VGate to Threshold VoltageV GS(TH) V GS = V DS , I D = 250 Gate Voltage Drain CurrentI DSS V DS = 95V, V GS = 0V--250 AV DS = x Rated BV DSS , V GS = 0V, T J = 150 o C--1000 AOn-State Drain Current (Note 2)I D(ON) V DS > I D(ON) x r DS(ON)MAX , V GS = 10V (Figure 7) to Source Leakage CurrentI GSS V GS = 20V-- 100nADrain to Source On Resistance (Note 2)r DS(ON) I D = , V GS = 10V (Figure 8, 9) Forward transconductance (Note 2)gfsV DS 50V, I D = (Figure 12) Delay Timet d(ON) V DD = 50V, I D , R G = 18 , R L = MOSFET Switching Times are Essentially Independent of Operating Temperature-913nsRise Timet r -3063nsTurn-Off Delay Timet d(OFF) -1870nsFall Timet f -2059nsTotal Gate Charge(Gate to Source + Gate to Drain)Q g(TOT) V GS = 10V, I D = , V DS = x Rated BV DSS , I g(REF) = (Figure 14) Gate Charge is Essentially Independent of OperatingTemperature-1030nCGate to Source ChargeQ gs to Drain Miller ChargeQ gd CapacitanceC ISS V DS = 25V, V GS = 0V, f = 1 MHz(Figure 11)-350-pFOutput CapacitanceC OSS -130-pFReverse Transfer CapacitanceC RSS -25- pFInternal Drain InductanceL D Measured From the Contact Screw On Tab To Center of DieModified MOSFET Symbol Showing the Internal Devices From the Drain Lead, 6mm ( )

4 From Package to Center of Source InductanceL S Measured From the Source Lead, 6mm ( ) From Header to Source Bonding Resistance Junction to CaseR JC o C/WThermal Resistance Junction to AmbientR JA Free Air Operation--80 o C/WLDLSDSG IRF520 2002 Fairchild Semiconductor CorporationIRF520 Rev. B Source to Drain Diode Specifications PARAMETERSYMBOLTEST CONDITIONSMINTYPMAXUNITS Continuous Source to Drain CurrentI SD Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Source to Drain Current (Note 3)I SDM --37 ASource to Drain Diode Voltage (Note 2)V SD T J = 25 o C, I SD = , V GS = 0V (Figure 13) Recovery Timet rr T J = 25 o C, I SD = , dI SD /dt = 100A/ Recovered ChargeQ RR T J = 25 o C, I SD = , dI SD /dt = 100A/ CNOTES:2. Pulse test: pulse width 300 s, duty cycle 2%.

5 3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).4. V DD = 25V, starting T J = 25 o C, L = 640mH, R G = 25 , peak I AS = Typical Performance Curves Unless Otherwise Specified FIGURE 1. NORMALIZED Power DISSIPATION vs CASE TEMPERATUREFIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATUREFIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCEGDSTC, CASE TEMPERATURE (oC)2550751001251501750 Power DISSIPATION , CASE TEMPERATURE (oC)507510017525108604ID, DRAIN CURRENT (A)2125150Z JC, , RECTANGULAR PULSE DURATION (s)PDMt1t210 NOTES:DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x Z JC + TCSINGLE IMPEDANCE (oC/W) IRF520 2002 Fairchild Semiconductor CorporationIRF520 Rev. BFIGURE 4. FORWARD BIAS SAFE OPERATING AREAFIGURE 5. OUTPUT CHARACTERISTICSFIGURE 6.

6 SATURATION CHARACTERISTICSFIGURE 7. TRANSFER CHARACTERISTICSFIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENTFIGURE 9. NORMALIZED DRAIN TO SOURCE ONRESISTANCE vs JUNCTION TEMPERATURET ypical Performance CurvesUnless Otherwise Specified (Continued) , DRAIN CURRENT (A)VDS, DRAIN TO SOURCE VOLTAGE (V)TC = 25oCTJ = MAX RATEDSINGLE PULSE 10 s100 s1ms10msOPERATION IN THISAREA IS LIMITEDBY rDS(ON)10 VVDS, DRAIN TO SOURCE VOLTAGE (V)200501512906ID, DRAIN CURRENT (A)VGS = 7V330 VGS = 6 VVGS = 8 VPULSE DURATION = 80 s1040 VGS = 5 VVGS = 4 VDUTY CYCLE = MAX151290612 3405ID, DRAIN CURRENT (A)VDS, DRAIN TO SOURCE VOLTAGE (V)3 VGS = 6 VVGS = 5 VVGS = 4 VVGS = 7 VVGS = 8 VVGS = 10 VPULSE DURATION = 80 sDUTY CYCLE = (ON), ON-STATE DRAIN CURRENT (A)VGS, GATE TO SOURCE VOLTAGE (V)11010175oC25oCVDS 50 VPULSE DURATION = 80 sDUTY CYCLE = MAXID, DRAIN CURRENT (A) (ON)

7 , DRAIN TO SOURCE ON RESISTANCEPULSE DURATION = 80 = 10 VVGS = 20 VDUTY CYCLE = , JUNCTION TEMPERATURE (oC)NORMALIZED ON -20204080 100140120160 180ID = , VGS = 10 VPULSE DURATION = 80 sDUTY CYCLE = MAXIRF520 2002 Fairchild Semiconductor CorporationIRF520 Rev. BFIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATUREFIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGEFIGURE 12. transconductance vs DRAIN CURRENTFIGURE 13. SOURCE TO DRAIN DIODE VOLTAGEFIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGET ypical Performance CurvesUnless Otherwise Specified (Continued) , JUNCTION TEMPERATURE (oC)NORMALIZED DRAIN TO VOLTAGE 60120ID = 250 AVDS, DRAIN TO SOURCE VOLTAGE (V)C, CAPACITANCE (pF)10008006004002000 VGS = 0V, f = 1 MHzCISS = CGS + CGDCRSS = CGDCOSS CDS + CGD110102 CISS COSS CRSS ID, DRAIN CURRENT (A)3691201554302gfs, transconductance (S)1TJ = 175oCTJ = 25oCPULSE DURATION = 80 sVDS 50 DUTY CYCLE = MAXTJ = 175oCISD, SOURCE TO DRAIN CURRENT (A)VSD, SOURCE TO DRAIN VOLTAGE (V) = 25oC1 PULSE DURATION = 80 sDUTY CYCLE = MAXQg, GATE CHARGE (nC)369120152080 VGS, GATE TO SOURCE VOLTAGE (V)4ID = = 20 VVDS = 50 VVDS = 80 VIRF520 2002 Fairchild Semiconductor CorporationIRF520 Rev.

8 BTest Circuits and Waveforms FIGURE 15. UNCLAMPED ENERGY TEST CIRCUITFIGURE 16. UNCLAMPED ENERGY WAVEFORMSFIGURE 17. SWITCHING TIME TEST CIRCUITFIGURE 18. RESISTIVE SWITCHING WAVEFORMSFIGURE 19. GATE CHARGE TEST CIRCUITFIGURE 20. GATE CHARGE LIAS+-VDSVDDRGDUTVARY tP TO OBTAINREQUIRED PEAK IAS0 VVDDVDSBVDSStPIAStAV0 VGSRLRGDUT+-VDDtONtd(ON)tr90%10%VDS90%10 %tftd(OFF)tOFF90%50%50%10%PULSE F12 VBATTERY50k VDSSDUTDGIg(REF)0( FCURRENTREGULATORID CURRENTSAMPLINGIG CURRENTSAMPLINGSUPPLY)RESISTORRESISTORSA ME TYPEAS DUTQg(TOT)QgdQgsVDS0 VGSVDDIG(REF)0 IRF520 DISCLAIMERFAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHERNOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILDDOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCTOR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENTRIGHTS, NOR THE RIGHTS OF following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and isnot intended to be an exhaustive list of all such SUPPORT POLICYFAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR used herein:1.

9 Life support devices or systems are devices orsystems which, (a) are intended for surgical implant intothe body, or (b) support or sustain life, or (c) whosefailure to perform when properly used in accordancewith instructions for use provided in the labeling, can bereasonably expected to result in significant injury to A critical component is any component of a lifesupport device or system whose failure to perform canbe reasonably expected to cause the failure of the lifesupport device or system, or to affect its safety STATUS DEFINITIONSD efinition of TermsDatasheet IdentificationProduct StatusDefinitionAdvance InformationPreliminaryNo Identification NeededObsoleteThis datasheet contains the design specifications forproduct development.

10 Specifications may change inany manner without datasheet contains preliminary data, andsupplementary data will be published at a later Semiconductor reserves the right to makechanges at any time without notice in order to datasheet contains final specifications. FairchildSemiconductor reserves the right to make changes atany time without notice in order to improve datasheet contains specifications on a productthat has been discontinued by Fairchild datasheet is printed for reference information orIn DesignFirst ProductionFull ProductionNot In ProductionOPTOLOGIC OPTOPLANAR PACMAN POP Power247 PowerTrenchQFET QS QT Optoelectronics Quiet Series SILENT SWITCHERFASTFASTr FRFET GlobalOptoisolator GTO HiSeC ISOPLANAR LittleFET MicroFET MicroPak MICROWIRE Rev.