JESD204 PHY v4 - Xilinx

1 JESD204 PHY IP Product GuideVivado Design SuitePG198 ( ) April 8, 2021 JESD204 PHY ( ) April 8, of ContentsIP FactsChapter 1: OverviewApplications .. 7 Licensing and Ordering Information .. 9 Chapter 2: Product SpecificationPerformance and Resource Utilization .. 10 Port Descriptions .. 10 AXI4-Lite Register Space .. 24 Line Rate Switching .. 41 Chapter 3: Designing with the CoreJESD204 PHY Configuration Options.. 54 General Design Guidelines .. 55 Clocking.. 56 Resets .. 57 Protocol Description .. 58 Chapter 4: Design Flow StepsCustomizing and Generating the Core .. 59 Constraining the Core .. 64 Simulation .. 65 Synthesis and Implementation .. 65 Chapter 5: Example DesignChapter 6: Test BenchAXI Interface.. 73 Appendix A: Verification, Compliance, and InteroperabilitySimulation.

2 74 Hardware Testing .. 74 Send FeedbackJESD204 PHY ( ) April 8, B: DebuggingFinding Help on .. 75 Debug Tools .. 76 Simulation Debug.. 78 Hardware Debug .. 79 Appendix C: Additional Resources and Legal NoticesXilinx Resources .. 80 Documentation Navigator and Design Hubs .. 80 References .. 81 Revision History .. 82 Please Read: Important Legal Notices .. 83 Send FeedbackJESD204 PHY ( ) April 8, SpecificationIntroductionThe Xilinx LogiCORE IP JESD204 PHY core implements a JESD204 physical interface to simplify sharing serial transceiver channels between transmit and receive cores. This core is not intended to be used standalone and should only be used only in conjunction with the JESD204 or JESD204C Designed to JEDEC JESD204B [Ref 1] and JEDEC JESD204C Draft [Ref 19] Supports 1 to 12 lane configurations Supports 1 to 12 lanes with JESD204 IP core and 1 to 8 lanes when using the JESD204C IP core Supports Subclass 0, 1, and 2 Physical Layer functions provided Supports transceiver sharing between TX and RX cores Optional AXI interface with AXI to DRP bridges for QPLL and Transceiver access(1) AXI interface enables line rate switching AXI register allows control of selected transceiver signalsIP Facts1.

3 Not available for GTP transceiver IP Facts TableCore SpecificsSupported Device Family(1)UltraScale+ , UltraScale Zynq -7000 SoC,Artix -7, Virtex -7, Kintex -7 Supported User InterfacesN/AResourcesPerformance and Resource Utilization webpageProvided with CoreDesign FilesRTLE xample Design VerilogTest Bench VerilogConstraints FileXDCS imulation ModelVerilogSupported S/W DriverN/ATested Design Flows(2)Design EntryVivado Design SuiteSimulationFor supported simulators, see theXilinx Design Tools: Release Notes SynthesisSupportRelease Notes and Known IssuesMaster Answer Record: 61911 All Vivado IP Change LogsMaster Vivado IP Change Logs: 72775 Xilinx Support web pageNotes: 1. For a complete list of supported devices, see the Vivado IP the supported versions of the tools, see theXilinx Design Tools: Release Notes FeedbackJESD204 PHY ( ) April 8, 1 OverviewThe LogiCORE IP JESD204 PHY core implements: A JESD204B Physical interface supporting line rates between and Gb/s on 1 to 12 lanes for 7 Series, UltraScale, and UltraScale+ devices.

4 A JESD204C Physical interface supporting line rates between and 32 Gb/s on 1 to 8 lanes for UltraScale and UltraScale+ the relevant User Guide for specific line rates supported by each device (Ta b l e 1 - 1):1. For certain UltraScale+ device speed grades, when using 8B10B line coding, the line rate might also be limited by the maximum frequency specified for TXUSRCLK/RXUSERCLK (core clock) with 40-bit Interconnect Logic Data width. The maximum line rate in these devices is TX/RXUSERCLK * 40. Refer to the relevant device data JESD204 PHY core can be configured with independent transmit and receive line rates and JESD204 standard version 1 1:Transceiver User Guides7 SeriesUltraScale UltraScale+ GTPE2 [Ref 12]GTHE3 [Ref 10]GTHE4 [Ref 10](1)GTXE2 [Ref 11]GTYE3 [Ref 13]GTYE4 [Ref 13](1)GTHE2 [Ref 11]GTYE2 Not SupportedSend FeedbackJESD204 PHY ( ) April 8, 1:OverviewThe following figure shows the JESD204 PHY core with shared logic in the example following figure shows a block diagram of the JESD204 PHY core with shared logic in the Target - Figure 1-1 Figure 1 1: JESD204 PHY Block Diagram Shared Logic in Example DesignX-Ref Target - Figure 1-2 Figure 1 2.

5 JESD204 PHY Block Diagram Shared Logic in CoreGT LaneGT LaneGT Lane<component_name>_gt_common_wrapper(QPLL) (optional)phyCtrlInterface (if AXI enabled)Serial I/Otxoutclkrxoutclktx_reset_donerx_reset _doneSerial I/OSerial I/Ocpll_refclktx_reset_gtdrpclkrx_reset_ gttx_core_clkrx_core_clkgtN_txgtN_txgtN_ txgtN_rxgtN_rxgtN_rxs_axi_aclktx_sys_res etrx_sys_reset<component_name>_gt<component_name>_block<component_name>(IP Core Top-Level)<component_name>_support<component_name>(IP Core Top-Level)<component_name>_support<component_name>_gt<component_name>_blockGT LaneGT LaneGT Lane<component_name>_gt_common_wrapper(QPLL) (optional)phyCtrlInterface (if AXI enabled)cpll_refclktx_reset_gtqpll_refcl kdrpclkrx_reset_gttx_core_clkrx_core_clk gtN_txgtN_txgtN_txgtN_rxgtN_rxgtN_rxSeri al I/Otxoutclkrxoutclktx_reset_donerx_reset _doneSerial I/OSerial I/Os_axi_aclktx_sys_resetrx_sys_resetSen d FeedbackJESD204 PHY ( ) April 8, 1:OverviewWhen used in conjunction with the JESD204 core, the JESD204 PHY core is a fully-verified solution design delivered by using the Xilinx Vivado Design Suite.

6 In addition, an example design is provided in Verilog. For more information, see the JESD204 LogiCORE IP Product Guide (PG066) [Ref 2]. ApplicationsThe JESD204 PHY core is a sub-core of both the JESD204 and JESD204C cores. For application information, see the JESD204 LogiCORE IP Product Guide (PG066) [Ref 2] and JESD204C LogiCORE IP Product Guide (PG242) [Ref 20]. Figure 1-3 shows a JESD204 PHY used in either a JESD204 or JESD204C Target - Figure 1-3 Figure 1 3: JESD204 PHY Used in a JESD204 /JESD204C SolutionJESD204 or JESD204C CoreSerial I/OJESD204 PHY CoreShared ClockingSend FeedbackJESD204 PHY ( ) April 8, 1:OverviewThe JESD204 PHY allows complex transceiver and JESD204 /JESD204C core sharing to be accomplished. The following figure, taken from Vivado IP integrator, shows three JESD204 PHY IPs sharing transceivers between three JESD204 IP cores and one JESD204C JESD204 PHY supports many use cases from the most common single JESD204 /JESD204C, single JESD204 PHY configuration to the extremely complex multi- JESD204 /JESD204C interleaved JESD204 PHY configurations.

7 See the JESD204 LogiCORE IP Product Guide (PG066) [Ref 2].X-Ref Target - Figure 1-4 Figure 1 4:IP Integrator Example Designjesd204_tx_0jesd204_tx_1jesd204_tx _2 JESD204 JESD204 JESD204jesd204_phy_0jesd204_phy_1 JESD204 PHYJESD204 PHYJESD204 PHYjesd204_phy_2conConcatAND3 Utility Reduced Logicjesd204_rxJESD204 Send FeedbackJESD204 PHY ( ) April 8, 1:OverviewLicensing and Ordering InformationThis Xilinx LogiCORE IP module is provided at no additional cost with the Xilinx Vivado Design Suite under the terms of the Xilinx End User License. Information about this and other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual Property page. For information about pricing and availability of other Xilinx LogiCORE IP modules and tools, contact your local Xilinx sales FeedbackJESD204 PHY ( ) April 8, 2 Product SpecificationThis chapter details the resource utilization and ports for the JESD204 PHY and Resource UtilizationFor details about performance and resource utilization, visit the Performance and Resource Utilization web core meets the performance specification of JESD204B/JESD204C.

8 The maximum serial line rate is limited by the maximum GTX/GTP/GTH/GTY line rate for the chosen device. See the appropriate device data sheet listed in Appendix DescriptionsThis section contains details about the JESD204 PHY following tables detail the ports available when the core is configured for either JESD204 or JESD204C, and also when the core is configured for shared logic in the core or in the example 2 1:Common Clock Ports - JESD204B Configurations (Shared Logic in Core)Signal NameI/ODescriptiontxoutclkOOutput clock from transceiver. This clock is sourced from the TX master channel, which is selected from the GUI in the JESD PHY clock from transceiver. This clock is sourced from the RX master channel, which is selected from the GUI in the JESD PHY output set to indicate the transceiver power is good.

9 This output is set after device configuration. This output is only available on UltraScale and UltraScale+ clock used to drive txusrclk2 of transceiver. In UltraScale and UltraScale+ devices txoutclk can be used to drive this FeedbackJESD204 PHY ( ) April 8, 2:Product Specificationrx_core_clkICore clock used to drive rxusrclk2 of transceiver. In UltraScale and UltraScale+ devices rxoutclk can be used to drive this Reconfiguration Port (DRP) clock for the Transceiver Channel clock for the Quad Common PLL in 7 clock for the Quad Common PLL(s) in UltraScale and UltraScale+ output from the QPLL (Quad M). Only present when QPLL clock output from the QPLL (Quad M). Only present when QPLL output from the QPLL (Quad M). Only present when QPLL is output from the PLL (Quad M).

10 Only present when PLL0 is clock input from the PLL (Quad M). Only present when PLL0 is output from the PLL0 (Quad M). Only present when PLL0 is output from the PLL (Quad M). Only present when PLL0 is clock output from the PLL (Quad M). Only present when PLL1 is output from the PLL1 (Quad M). Only present when PLL1 is output from the QPLL (Quad M). Only present when QPLL0 is clock output from the QPLL (Quad M). Only present when QPLL0 is output from the QPLL0 (Quad M). Only present when QPLL0 is output from the QPLL (Quad M). Only present when QPLL1 is clock output from the QPLL (Quad M). Only present when QPLL1 is output from the QPLL1 (Quad M). Only present when QPLL1 indicating that the internal MMCM has locked. Signal can be shared with other IP using the same clocks.