KCU105 Board User Guide - Xilinx

1 KCU105 BoardUser GuideUG917 ( ) February 6, 2019 KCU105 Board User Guide2UG917 ( ) February 6, HistoryThe following table shows the revision history for this Electrostatic Discharge Caution. Added memory component information in DDR4 Component Memory. Replaced pin AM9 with D28 in Table 1-13. Revised appendix title and removed constraints file listing in Appendix D, Xilinx Design Constraints. Updated Markings in Appendix G, Regulatory and Compliance system Clock Source and Table Table 1-22 and Table 1-23. Added Documentation Navigator and Design Programmable User Clock Source, FMC HPC Connector J22, FMC LPC Connector J2, and Switches. Revised Figure Table Figure 1-21. Changed the IOSTANDARD LVCMOS18 line in KCU105 Board Constraints File Listing on page 120. Added Board thickness to Dimensions.

2 Updated the Declaration of FMC HPC Connector J22. Revised Figure 1-23. Updated the binary format for I2C EEPROM in Table 1-19. Updated the clocks constraints file listing in Appendix D, Master Constraints File connectivity information for Quad 226, Quad 227, and Quad 228 in GTH Transceivers. Updated Figure 1-21 and Figure 1-36. Updated HDMI Video Output, including updating Figure 1-22 and Table typographical Table 1-17, Table 1-21, and Figure the Si5328C clock multiplier/jitter attenuator to Si5328B throughout, including updating the frequency range. Added impedance and insertion loss information to GTH SMA Clock Input, GTH TX and RX SMA Differential Pairs, PCI Express Endpoint Connectivity, SFP/SFP+ Module Connectors, FMC HPC Connector J22, and FMC LPC Connector J2. Updated Figure 1-2, Figure 1-8, Figure 1-9, Figure 1-22, Figure 1-23, Figure 1-29, Figure 1-34, Figure 1-36, Figure A-1, Figure C-1, and Figure C-2.

3 Changed IIC to I2C throughout. Updated Table 1-4 and Table 1-25. Added Table 1-26, Maxim Power Tool GUI Regulator Settings. Updated information for J11, J47, and J49 in Table A-2. Updated callout number in KCU105 Board Zynq-7000 SoC XC7Z010 system Controller. Added instructions for accessing the system controller main menu in Appendix C, system Controller. Updated Clock Menu section. Updated the KCU105 Board Constraints File Listing in Appendix D. Updated the KCU105 evaluation kit master answer record Xilinx FeedbackKCU105 Board User Guide3UG917 ( ) February 6, of ContentsRevision History .. 2 Chapter 1: KCU105 Evaluation Board FeaturesOverview .. 6 KCU105 Evaluation Board Features .. 6 Board Diagram .. 8 Feature Descriptions .. 9 Electrostatic Discharge Caution .. 9 Kintex UltraScale XCKU040-2 FFVA1156E Device.

4 13 DDR4 Component Memory .. 18 Dual Quad-SPI Flash Memory .. 22 Micro-SD Card Interface .. 25 USB JTAG Interface .. 27 FMC Connector JTAG Bypass .. 28 Clock Generation .. 28 GTH Transceivers .. 39 PCI Express Endpoint Connectivity .. 45 SFP/SFP+ Module Connectors .. 4710/100/1000 Mb/s Tri-Speed Ethernet PHY .. 49 Ethernet PHY Status LEDs .. 51 Dual USB-to-UART Bridge .. 52 HDMI Video Output .. 54I2C Bus, Topology, and Switches .. 57 Status and User LEDs .. 59 User I/O .. 60 Switches .. 68 FPGA Mezzanine Card Interface .. 71 KCU105 Board Power system .. 79 FMC VADJ_1V8 Power Rail .. 81 Monitoring Voltage and Current .. 82 SYSMON Power system Measurement .. 82 Cooling Fan .. 87 KCU105 Board Zynq-7000 SoC XC7Z010 system Controller .. 87 Appendix A: Default Switch and Jumper SettingsSwitches.

5 89 Jumpers.. 90 Appendix B: VITA FMC Connector PinoutsOverview .. 92 Send FeedbackKCU105 Board User Guide4UG917 ( ) February 6, C: system ControllerOverview .. 94 Power-On and Reset .. 97 KCU105 On- Board Clocks .. 97 Clock Menu .. 97 PMBus Menu .. 102 PMBus Menu Options ..102 SYSMON Menu .. 104 SYSMON Menu Options ..105 FMC Menu .. 107 FMC Menu Options ..108 GPIO Menu .. 115 GPIO Menu Options ..115 EEPROM Menu .. 116 EEPROM Menu Options ..116 CONFIG Menu.. 117 CONFIG Menu Options ..117 UltraScale FPGA User Design Considerations .. 118 Appendix D: Xilinx Design ConstraintsOverview .. 119 Appendix E: Board SetupInstalling the KCU105 Board in a PC Chassis .. 120 Appendix F: Board SpecificationsDimensions .. 122 Environmental .. 122 Temperature.

6 122 Humidity ..122 Operating Voltage ..122 Appendix G: Regulatory and Compliance InformationOverview .. 123CE Directives .. 123CE Standards.. 123 Electromagnetic Compatibility ..123 Safety ..124 Markings .. 124 Appendix H: Additional Resources and Legal NoticesXilinx Resources .. 125 Solution Centers .. 125 Send FeedbackKCU105 Board User Guide5UG917 ( ) February 6, Navigator and Design Hubs .. 125 References .. 126 Please Read: Important Legal Notices .. 128 Send FeedbackKCU105 Board User Guide6UG917 ( ) February 6, 1 KCU105 Evaluation Board FeaturesOverviewThe KCU105 evaluation Board for the Xilinx Kintex UltraScale FPGA provides a hardware environment for developing and evaluating designs targeting the UltraScale XCKU040-2 FFVA1156E device. The KCU105 evaluation Board provides features common to many evaluation systems, including a DDR4 component memory, a high definition multimedia interface (HDMI ), two small form-factor pluggable (SFP+) connectors, an eight-lane PCI Express interface, an Ethernet PHY, general purpose I/O, and two UART interfaces.

7 Other features can be added by using VITA-57 FPGA mezzanine cards (FMCs) attached to the low pin count (LPC) FMC and high pin count (HPC) FMC Evaluation Board FeaturesThe KCU105 evaluation Board features are listed here. Detailed information for each feature is provided in Feature Descriptions. Kintex UltraScale XCKU040-2 FFVA1156E device Zynq SoC XC7Z010 based system controller 2 GB DDR4 component memory (four [256 Mb x 16] devices) Dual 256 Mb Quad serial peripheral interface flash memory (Dual Quad SPI) Micro secure digital (SD) connector USB JTAG interface via Digilent module with micro-B USB connector Clock sources: Si5335A quad fixed frequency clock generator (300 MHz, 125 MHz, 90 MHz, MHz) Si5328B clock multiplier and jitter attenuator (8 kHz - 808 MHz) Si570 I2C programmable LVDS clock generator (10 MHz - 810 MHz) Subminiature version A (SMA) connectors (differential) 20 GTH transceivers (five Quads) FMC HPC connector (eight GTH transceivers)Send FeedbackKCU105 Board User Guide7UG917 ( ) February 6, 1.

8 KCU105 Evaluation Board Features FMC LPC connector (one GTH transceiver) 8-Lane PCI Express (eight GTH transceivers) Two SFP+ connectors (two GTH transceivers) TX and RX pair SMA connectors (one GTH transceiver) PCI Express endpoint connectivity Gen1 8-lane (x8) Gen2 8-lane (x8) Gen3 8-lane (x8) Two SFP+ connectors Ethernet PHY SGMII interface with RJ-45 connector Dual USB-to-UART bridge with micro-B USB connector HDMI codec with HDMI connector I2C bus Status LEDs User I/O Program_B pushbutton Pmod Headers VITA FMC HPC connector J22 VITA FMC LPC connector J2 Power on/off slide switch SW1 Power management with PMBus voltage monitoring through Maxim power controllers and GUI, current monitoring via the FPGA SYSMON block Single 10-bit MSPS SYSMON analog-to-digital converter Configuration options: Dual Quad-SPI flash memory USB JTAG configuration port (Digilent module) Platform cable header J3 JTAG configuration port system controller micro-SD cardSend FeedbackKCU105 Board User Guide8UG917 ( ) February 6, 1.

9 KCU105 Evaluation Board FeaturesBoard DiagramThe KCU105 Board diagram is shown in Figure 1-1X-Ref Target - Figure 1-1 Figure 1-1: KCU105 Evaluation Board Block DiagramJTAG ModuleandJTAG HeaderPage 16 Dual Quad-SPIF lash MemoryPage 39 DDR4 Memory 4 x 256 Mb x 16 SDRAMP ages 17-20 ConfigurableClocksPage 35 RecoveredClockSi5328 Page 37 Sysclk (300 MHz)Generator Si5335 Page 34U1 XCKU040-2 FFVA1156 EProgrammable LogicPCIex 8-LanePage 26SD CardConnectorPage 33 FMC HPCC onnectorPages 21-24 FMC LPCC onnectorPage 25 MechanicalPage 6610/100/1,000 Ethernet PHY(SGMII only)Page 38 USB UARTandConnectorPage 40 HDMI CodecandConnectorPages 46, 47 PmodHeadersPage 48 XADCH eaderPage 35 system ControllerXC7Z010 CLG225 Pages 29-31I2C MultiplexerandI2C EEPROMP ages 49,402 x SFP+Pages 27,28 SwitchesLEDs andPushbuttonsPage 41 MGT SMAGPIO SMAPage 36 Note.

10 Page numbers reference the page number of schematic 0381556X18365-113016 Send FeedbackKCU105 Board User Guide9UG917 ( ) February 6, 1: KCU105 Evaluation Board FeaturesFeature DescriptionsFigure 1-2 shows the KCU105 Board . Each numbered feature that is referenced in Figure 1-2 is described in Table 1-1 with a link to detailed information provided under Feature :Figure 1-2 is for visual reference only and might not reflect the current revision of the Discharge CautionCAUTION!ESD can damage electronic components when they are improperly handled, and can result in total or intermittent failures. Always follow ESD-prevention procedures when removing and replacing prevent ESD damage: Use an ESD wrist or ankle strap and ensure that it makes skin contact. Connect the equipment end of the strap to an unpainted metal surface on the chassis.