Lab 3 Layout Using Virtuoso Layout XL (VXL)

1 1 Lab 3 layout using virtuoso layout xl (VXL) This Lab will go over: 1. Creating Layout with Virtuoso Layout XL (VXL). 2. Transistor Chaining. 3. Creating Standard cell. 4. Manual Routing 5. Providing Substrate or Bulk Connection. 1. Creating Layout with Virtuoso Layout XL (VXL) We will be Using PCELLs developed by NCSU to Layout a 2 inputs nand gate, denoted as nand2. If you are not running CDS tools, do so according to Lab 1. First we need to create a Layout view of our nand2. Go to the library manager and execute (LM)File>New>Cell A pop-up like Figure 1 should appear.

2 Fill out the pop-up exactly as in Figure 1, then click OK. The Virtuoso Layout editor (VLE) will open as shown in Figure 2. Figure 1: Creating Layout view of nand2 2 Figure 2: Virtuoso Layout Editor (VLE) 3 Figure 3: LSW The Layer Select Window (LSW) will also open as shown in Figure 3. This window shows all the available layers that you can use in creating your Layout in the AMI06 process. If you don t see it, it may be hidden under another window. Re-size each window and re-arrange so that window will be visible.

3 4 To make sure that all layers will appear in LSW, execute (VLE) Options> A pop-up will display as in Figure 4, make sure in the Array Display area that the Full radio button is selected. Note that X snap spacing and Y snap spacing should indicate lambda ( * )=.15 for AMI06 process. Set the pop-up according to Figure 4 and click OK. Figure 4: Setting Display Options We will be Using the Virtuoso Layout XL (VXL), to help us in creating the Layout . This is a schematic driven Layout . To invoke VXL, in the Layout editor execute (VLE) Launch>LayoutXL.

4 A schematic window showing nand2 schematic will display as shown in Figure 5. 5 Figure 5: Nand2 schematic To put the components shown in the schematic window into the Layout editor, execute (VXL) connectivity>Generate> All from A pop-up will display as in Figure 6. Note all signal I/O pins must be on metal2 layer, power rails (mygnd and myvdd) must be on metal1 layer, and default layer on metal2. In addition, the Create button for mygnd and myvdd must be de-selected. This means that we will do our own placement of mygnd and myvdd.

5 Metal2 is needed for signal I/O pins, to enable the downstream automatic Layout generator to successfully Layout of a 2-input exclusive or gate (xor2), which consists of inverters and nand2 gates to be discussed in lab 5. Complete the pop-up exactly as shown in Figure 6, then click OK. 6 Figure 6: Display Pin Name Option pop-up 7 The initial component and pin placement is displayed in Figure 7. The components and pins are shown outside a bounding box. This bounding box is an estimate of the optimum size of the final Layout . Automatic router to be discussed in Lab 5 will use the bounding box to constraint all routing to occur within the box.

6 The bounding box may need to be re-sized to satisfy our goal of creating standard cells. Standard cells are cells that are created to have the same height, so that when abutting two standard cells both power rails will connect. Figure 7: Initial component and pin placement 8 Place the component and pin within the bounding box in their relative position as in the schematic, execute. For that execute the (VXL) connectivity->Generate->Place as in Schematic. Figure 8 shows the resulting placement within the bounding box.

7 The bounding box size was estimated based on 4 individual transistors. In this lab, we will introduce transistor chaining, a process of combining two transistors of the same type to share a common substrate. Figure 8 shows the components in level 0 (outline only). To display all levels, press (Shift) f key. To go back to level 0, press (Ctrl) f key. 9 Figure 8: Component and pin placement within the bounding box 2. Transistor Chaining Figure 9 shows the two pmos transistors with all layers prior to chaining. To determine how chaining should be done, we must first determine how the transistors are interconnected.

8 This is achieved by selecting a transistor (by clicking on it), then put and click the cursor on the selected transistor until the cursor change to four arrow icon, move the transistor. As you move the transistor, flight line in bright yellow will appear indicating its interconnection. For chaining the two parallel pmos transistors, we want to combine the drain of transistor M0 and M1 as shown in the schematic. The drain of M0 and M1 are both connected to output pin Y. Most likely the initial transistor configuration will be as follows: M1=|S1|G1|D1| and M0=|S0|G0|D0|.

9 In chaining we like to combine D1 and D0. To achieve this, we need to flip transistor M0, so that its new configuration becomes M0=|D0|G0|S0|. So that after transistor chaining, the combine transistor configuration of M1M0 is |S1|G1|D1/ D0 |G0|S0. To flip transistor M0, first select M0 then execute (VXL)Edit> A move pop-up will open with three buttons: Rotate (Rotate 90 CCW), Sideways (Flip horizontally), and Upside Down (Flip Vertivally). Select Sideways to flip horizontally. Figure 10 shows the result of flipping M0 and chaining M0 and M1.

10 The chaining is achieved by aligning the contacts. To make sure that the chaining process is properly done perform a DRC check by executing (VXL)Verify> A pop-up will display, accept the default setting by clicking OK. Check the CIW window for no error message. If there are errors, they will be highlighted in the VXL window. Correct them before proceeding. 10 Figure 9: The two parallel pmos cells prior to chaining 11 Figure 10: Two pmos cells after chaining 12 Similarly chain the two series connected nmos transistors, M3 and M2. In the schematic, it shows that we need to combine or chain the source of M3 (S3) and the drain of M2(D2).