LPDDR3 and LPDDR4 - JEDEC

1 LPDDR3 and LPDDR4 : How Low-Power DRAM Can Be Used in High-Bandwidth Applicationsin High-Bandwidth ApplicationsMobile Forum 2013 Marc GreenbergDirector, Product MarketingSynopsysCopyright 2013 SynopsysAgendaAgenda High-Bandwidth, Low-Power DRAM Today Using Dual Personality Memories Effectively to Reduce Power Consumption System Environment Around LPDDR Devices Future DirectionHigh Bandwidth TodayHigh Bandwidth Today Shipping Application Processors Up to 4 channel LPDDR2 2 channel LPDDR3 -1600 LPDDR3 in mass production per LPDDR3 in mass production per manufacturer websites One and two channel LPDDR3 -1600 up to 4 die package with 4 Gbit density Early access status for LPDDR3 -2133 speedsSources: ' s requirementsToday s low-powerDRAM devicesGByte/secpeak bandwidthPotential future low-powerDRAM devicesHow Potential Future Devices CompareHow Potential Future Devices Compare010* No published JEDEC standard exists.

2 Standard publication is dependent on JEDEC process. Specification or performance is subject to change without notice. Part availability dependent on manufacturer.*HighHigh--Bandwidth Interface ExamplesBandwidth Interface Examples PCI Express Gen3 1GB/s (8Gb/s) (5Gb/s) HDMI (4k) 1GB/s (8Gb/s) LPDDR4 parallel No embedded clock 14GB/s/channelLP DRAM Bandwidth DriversLP DRAM Bandwidth DriversLPDDR4 What is Low Power?What is Low Power? Laptop with a 90 Watt-hour battery? Tablet with a 40 Watt-hour battery? Phone with a 5-10 Watt-hour battery? Phone with a 5-10 Watt-hour battery?Reducing Power in DRAMR educing Power in DRAM DRAM core power usage Generally a function of device organization, usage, manufacturing technology Standby power Standby power Available features for controlling power IO signaling power Function of voltage swing, termination, IO capacitance, frequency, load.

3 Power dependent on energy per bit (TBD) and system configurationLet s Call Let s Call IIt Less Power t Less Power 3mW/Gbps (3pJ/bit) is a great figure of merit per Bit(pJ/bit = mW/Gbit/sec)2-channelLPDDR432002-channel LPDDR442664-channel LPDDR432004-ChannelLPDDR44266 Not including: Memory core power, address/control bus, PHY power, memory controller or any computation that the target system might be operating the accessing the etc. merit ) Power Low Power MMeets High Bandwidtheets High Bandwidth Multiple personality devices Low power, low bandwidth mode Extensive standby modes Infrequent full bandwidth usage Infrequent full bandwidth usageNormal OperationNormal Operation Low-speed operation < DDR1600, unterminated Using all LPDDR power reduction Using all LPDDR power reduction capabilities when idleWhen Can You When Can You GGo o FFull ull SSpeed? peed? When plugged in During time-bound occasional operations operations Boot Program launch Image/video processing to run full speedRequirements to run full speed Available power Sufficient cooling Fully Trained interface Fully Trained interface On-Die Termination Temperature Monitoring Memory controller and PHY in high-speed modeTermination Termination -- HighHigh--Speed ModeSpeed Mode510ps620ps320ps 28nm silicon results Data eye measured at Write ball Wirebond package Worst case SSOLPDDR2-1066 UnterminatedDDR3-1600 TerminatedLPDDR3-1600 UnterminatedSource: SynopsysFinding the Ideal PCB EnvironmentFinding the Ideal PCB Environment PoP provides very short electrical connection forconnection forhigh speed andlow power But power dissipation limitedFinding the Ideal PCB EnvironmentFinding the Ideal PCB Environment Another option.

4 Clamshell Used in Synopsys characterization Seen in at least one tablet Seen in at least one tabletTop sideBottom sidePCBA pplication ProcessorDRAMS chematic side viewMemory Partitioning ConceptMemory Partitioning ConceptChannel 1 Rank 0 High Resolution Video Processing, Image Processing, etcChannel 0 Rank 0 Modem, OS Kernel, Running appsMaximum bandwidthAll chips activeChannel 1 Rank 1 High Resolution Video Processing, Image Processing, etcChannel 0 Rank 1 Stalled/Sleeping AppsChannel 0 Channel 1 Application ProcessorMemory Partitioning ConceptMemory Partitioning ConceptChannel 1 Rank 0 High Resolution Video Processing, Image Processing, etcChannel 0 Rank 0 Modem, OS Kernel, Running appsNo videoRunning appsCh0 activeChannel 1 Rank 1 High Resolution Video Processing, Image Processing, etcChannel 0 Rank 1 Stalled/Sleeping AppsChannel 0 Channel 1 Application ProcessorMemory Partitioning ConceptMemory Partitioning ConceptChannel 0 Rank 0 Modem, OS Kernel, Running appsNo videoLow activityCh0 R1 activeChannel 1 Rank 0 High Resolution Video Processing, Image Processing, etcChannel 0 Rank 1 Stalled/Sleeping AppsChannel 1 Application ProcessorChannel 0 Channel 1 Rank 1 High Resolution Video Processing, Image Processing, etcMemory Partitioning ConceptMemory Partitioning ConceptChannel 0 Rank 0 Modem, OS Kernel, Running appsBasic keep alive AOACLow frequencyCh0 R1 activeChannel 1 Rank 0 High Resolution Video Processing, Image Processing, etcChannel 0 Rank 1 Stalled/Sleeping AppsChannel 0 Channel1 Application ProcessorChannel 1 Rank 1 High Resolution Video Processing, Image Processing, etcMemory Partitioning ConceptMemory Partitioning ConceptChannel 0 Rank 0 Modem, OS Kernel.

5 Running appsComplete standbyChannel 1 Rank 0 High Resolution Video Processing, Image Processing, etcChannel 0 Channel 0 Rank 1 Stalled/Sleeping AppsChannel1 Channel 1 Rank 1 High Resolution Video Processing, Image Processing, etcApplication ProcessorSummary of LowSummary of Low--Power DRAM Power DRAM Interface TechniquesInterface Techniques Select a low-power DRAM Use DRAM low-power features Frequency scaling Switching termination on/off Switching termination on/off DRAM clock gating Partitioning memory into DRAM On-chip power control for AP Clock gating, power gating (esp. DDR IOs), DVFS s requirementsToday s low-powerDRAM devicesGByte/secpeak bandwidthPotential future low-powerDRAM devicesHow Potential Future Devices CompareHow Potential Future Devices Compare010* No published JEDEC standard exists. Standard publication is dependent on JEDEC process. Specification or performance is subject to change without notice.

6 Part availability dependent on manufacturer.*ConclusionsConclusions Future DRAM bandwidth will continue to increase Power is reduced in LPDDR4 , but still proportional to bandwidthproportional to bandwidth Use multiple techniques to meet performance and power goals of high-bandwidth low-power DRAMT hank YouThank YouMarc GreenbergDirector, Product MarketingSynopsysCopyright 2013 SynopsysMobile Forum 2013