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Master Learning Maps - cadence.com

Cadence Training Services Learning maps provide a comprehensive visual overview of the Learning opportunities for Cadence customers. They provide recommended course flows as well as tool experience and knowledge levels to guide students through a complete Learning plan. Learning Maps cover all Cadence technologies and reference courses available worldwide. For course names, descriptions, and schedules, please select the Browse Catalog button Maps PCB Design and Analysis Custom IC, Analog, and RF Design Digital Design and Signoff System Design and Analysis IC Package Design and Analysis Tensilica Processor IPSigrityAuroraOrCAD Capture Constraint Manager PCB FlowAllegro System Architect Allegro Design Entry HDL Front-to-Back FlowLogic DesignAdvanced BeginnerAdvanced BeginnerAllegro Design Reuse Allegro AMS Simulator Allegro AMS Simulator Advanced AnalysisAllegro Design Entry HDL Basics Allegro PCB Editor Basic TechniquesAllegro PCB Editor Intermediate TechniquesAllegro PCB Router BasicsAllegro PCB Editor Advanced MethodologiesAllegro Update TrainingEssential High-Speed PCB Design for Signal IntegrityPCB Design at RF Multi-Gigabit Transmission, EMI Control, and PCB MaterialsAllegro Sigrity SI FoundationsLearning Map Digital Design and Sig

Cadence Training Services learning maps provide a comprehensive visual overview of the learning opportunities for Cadence customers. They provide recommended course flows as well as tool experience and knowledge levels to guide students through a complete learning plan. ... Using OrCAD ® Capture OrCAD CIS ...

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Transcription of Master Learning Maps - cadence.com

1 Cadence Training Services Learning maps provide a comprehensive visual overview of the Learning opportunities for Cadence customers. They provide recommended course flows as well as tool experience and knowledge levels to guide students through a complete Learning plan. Learning Maps cover all Cadence technologies and reference courses available worldwide. For course names, descriptions, and schedules, please select the Browse Catalog button Maps PCB Design and Analysis Custom IC, Analog, and RF Design Digital Design and Signoff System Design and Analysis IC Package Design and Analysis Tensilica Processor IPSigrityAuroraOrCAD Capture Constraint Manager PCB FlowAllegro System Architect Allegro Design Entry HDL Front-to-Back FlowLogic DesignAdvanced BeginnerAdvanced BeginnerAllegro Design Reuse Allegro AMS Simulator Allegro AMS Simulator Advanced AnalysisAllegro Design Entry HDL Basics Allegro PCB Editor Basic TechniquesAllegro PCB Editor Intermediate TechniquesAllegro PCB Router BasicsAllegro PCB Editor Advanced MethodologiesAllegro Update TrainingEssential High-Speed PCB Design for Signal IntegrityPCB Design at RF Multi-Gigabit Transmission, EMI Control.

2 And PCB MaterialsAllegro Sigrity SI FoundationsLearning Map Digital Design and SignoffPCB Design and Analysis Learning Map 2020 Cadence Design Systems, Design Entry using OrCAD CaptureOrCAD CISA llegro Team Design Authoring Analog Simulation with PSpice Analog Simulation with PSpice Advanced AnalysisPCB DesignSI/PI AnalysisAllegro Sigrity PISigrity PowerDC and OptimizePI TopXplorerSystemSIfor Parallel Bus and Serial Link AnalysisLibrary DevelopmentAllegro PCB LibrarianAllegro EDM PCB LibrarianAllegro Design Entry HDL SKILL Programming LanguageAllegro PCB Editor SKILL Programming LanguageAdvanced Design Verification with the RAVEL Programming LanguageModel Generation and Analysis using PowerSI, Broadband SPICE and 3D-EMAllegro High-Speed Constraint ManagementAllegro System CaptureNew Course Number of days for instructor-led course Tiers of Cadence products used in courseOnline Course AvailableDigital Badge AvailableAllegro EDMD esign Entry HDL Front-to-Back FlowClarity 3D SolverCelsius Thermal SolverAdvanced BeginnerAdvanced BeginnerSiP LayoutAllegro Package DesignerAllegro Sigrity Package Assessment and Model Extraction OrbitIO System PlannerLearning Map Digital Design and SignoffIC Package Design and Analysis Learning MapIC Package DesignSI/PI AnalysisAdvanced Design Verification with the RAVEL Programming LanguageAllegro Sigrity SI FoundationsAllegro Sigrity PISigrity PowerDC and OptimizePI TopXplorerSystemSIfor Parallel Bus

3 And Serial Link AnalysisModel Generation and Analysis using PowerSI, Broadband SPICE,and 3D-EM Allegro FPGA System PlannerNew Course Number of days for instructor-led course Tiers of Cadence products used in course 2020 Cadence Design Systems, Course AvailableClarity 3D SolverCelsius Thermal SolverAllegro Package Designer PlusS2 ADE Assembler & Multi Test Corner AnalysisReal Modeling withSystemVerilogBehavioral Modeling with VHDL-AMSC ommand-Line Based Mixed-Signal Simulations w/ XceliumUse ModelAdvanced BeginnerAdvanced BeginnerCircuit Design, Simulation, Modeling and RF DesignLearning Map Digital Design and SignoffCustom IC, Analog and RF Design Learning MapMixed-Signal Simulations using Spectre AMS Designer Analog Modeling with Verilog-A Behavioral Modeling withVerilog AMSReal Modeling with Verilog-AMS S1 Spectre BasicsSpectre Simulator Fundamentals SeriesS2 Large-Signal S3 Small-SignalS4 Spectre MDLD esign Checks and AssertsSpectre Accelerated Parallel Simulator (APS)

4 Virtuoso Spectre Pro SeriesS1 DC AlgorithmS2 AC, XF, STB, Noise S3 Transient AlgorithmS4 Fourier TransformS5 Transient NoiseSpectre RF Shooting NewtonVirtuoso Schematic Editor S1 Setup, Run, & View Verifier Results1 of 2 see next pageSpectre XPS for Mixed-Signal DesignsNew Course Number of days for instructor-led course Tiers of Cadence products used in course 2020 Cadence Design Systems, Course AvailableDigital Badge AvailableS1 ADE Explorer & Single Test Corner AnalysisVirtuoso ADE Explorer & Assembler SeriesS3 Sweeping Variables and Simulating CornersS4 Monte Carlo, Real-Time Tuning & Run PlansS2 Reference Flow and Analog Coverage using the Setup Library AssistantVirtuoso ADE Verifier SeriesVirtuoso Visualization and AnalysisSpectre RF Harmonic BalanceSystemVerilog Real Number Modeling (SV-RNM) Based Advanced Verification5G mmWaveHandset System Design S1 RFIC (Transceiver) DesignAdvanced BeginnerAdvanced BeginnerSKILL Language ProgrammingSKILL Language Programming IntroductionT1: Env.

5 And Basic CommandsIC CADL ayout Design and Advanced NodesLayout VerificationLearning Map Digital Design and SignoffCustom IC, Analog and RF Design Learning MapSKILL Development of Parameterized CellsAdvanced SKILL Language ProgrammingVirtuoso Layout Design BasicsVirtuoso Connectivity-Driven Layout Transition T2: Create and Edit CommandsT3: Basic CommandsT4: Advanced CommandsT5: Interactive Routing T6: Constraint-Driven Flow and Power RoutingT7: Module Generator and FloorplannerT8: Debugging Layout IssuesVirtuoso FloorplannerVirtuoso Abstract GeneratorVirtuoso Space-Based Router Virtuoso Space-Based Router ExpressVirtuoso Layout for Adv. Nodes Virtuoso Layout Pro SeriesVirtuoso Advanced-Node ICADVP hysicalVerification System (PVS)PhysicalVerification Language Rules-WriterT1: Place and RouteT2: ElectromigrationT1: Overview and Technology Setup T2: ParasiticExtraction T3: Extracted View Flows and Advanced Features Quantus Extraction Solution Transistor-LevelSeries2of 2 see prior pageNew Course Number of days for instructor-led course Tiers of Cadence products used in course 2020 Cadence Design Systems, Course AvailableDigital Badge AvailableT9.

6 Virtuoso Design PlannerEPegasusVerification SystemVirtuoso Advanced-NodeandMethodology -ICADVMV irtuoso Layout for Advanced Nodes and Methodology PlatformEEVirtuoso Simulation Driven Routing (SDR)ETest Synthesis with Genus Stylus Common UICadence RTL-to-GDSII FlowAdvanced BeginnerAdvanced BeginnerVirtuoso Digital ImplementationInnovus Implementation System(Block)Innovus Implementation System (Hierarchical)Low-Power Flow with Innovus Implementation SystemInnovus Clock Concurrent Optimization Technology for Clock Tree SynthesisBasic Static Timing AnalysisTempus Signoff Timing Analysis and ClosureVoltus Power-Grid Analysis and SignoffConformal Equivalence CheckingConformal Low-Power Verification ConformalECOS ynthesis and TestImplementationSilicon SignoffEquivalence CheckingLearning Map Digital Design and SignoffDigital Design and Signoff Learning MapJoules Power CalculatorFundamentals of IEEE 1801 Low-Power Specification FormatModus DFT Software SolutionAdvanced Synthesis with Genus Stylus Common UI Genus Synthesis Solution withStylus Common UILow-Power Synthesis Flow with Genus Stylus Common UINew Course Number of days for instructor-led course 2020 Cadence Design Systems, Course AvailableDigital Badge AvailableDesign For Test FundamentalsConformal Low-Power Verification using IEEE1801 Simulation.

7 Coverage and DebugSpecman Fundamentals for Block-Level Environment Developers SpecmanAdvanced Verification Advanced BeginnrXceliumFaultSimulatorAdvanced BeginnerAdvanced BeginnerSystem Design and Verification Learning MapNew Course Number of days for instructor-led course Tiers of Cadence products used in course 2020 Cadence Design Systems, Course AvailableVIP Basic Building Blocks and UsagePerspec System Verifier -BasicCadence RTL-To-GDSII FlowFoundations of Metric-Driven VerificationMetric-Driven Verification using vManager vManagerTool Usage in Batch ModeLow-Power Simulation with IEEE1801 UPFLow-Power Simulation with CPF XceliumIntegrated CoverageXcelium Simulator Digital Badge AvailableAdvanced BeginnerAdvanced BeginnerLearning Map Digital Design and SignoffSystem Design and Verification Learning MapDesign and Verification LanguagesVerilog Language and ApplicationSystemC Language FundamentalsC++ Language Fundamentals for Design and VerificationSystemCTransaction-Level Modeling Verification using UVMS ystemVerilog Advanced Register Verification using UVMS ystemCSynthesis with

8 Stratus HLS Real Modeling with Verilog AMS Real Modeling with SystemVerilogPerl for EDA EngineeringTcl Scripting for EDAVHDL Language and ApplicationSystemVerilog for Design and VerificationSystemVerilogAssertionsNew Course Number of days for instructor-led course Tiers of Cadence products used in course 2020 Cadence Design Systems, Course AvailableEssential SystemVerilogfor UVM (optional)JasperGold Formal ExpertSVA, Formal & JasperGold Fundamentals for DesignersJasperGold Formal Fundamentals UVMD igital Badge AvailableSystemVerilog Real Number Modeling (SV-RNM) Based Advanced VerificationLearning Map Digital Design and SignoffTensilicaProcessor IP Learning MapTensilica Xtensa LX Processor FundamentalsTensilica Instruction Extension Language and DesignTensilica Xtensa LX Processor InterfacesTensilica Xtensa LX Hardware Verification and EDAT ensilicaConnX BBE64EP Baseband EngineTensilica ConnX BBE16EP BasebandEngineTensilica ConnX BBE32EP Baseband EngineConnXDSPT ensilica XtensaLX Fusion DSPHiFiAudio DSPV ision DSP Tensilica Fusion G6 DSPT ensilica Fusion F1 DSPT ensilica Fusion G3 DSPT ensilica HiFi 3 Audio Engine ISAT ensilica Audio Codec APIT ensilica HiFi 2/EP/Mini Audio Engine ISAT ensilica DNA 100 Architecture and ProgrammingTensilica Vision P5 DSPT ensilica Vision P6 DSPT ensilica HiFi 4 DSPNew Course Number of days for instructor-led course 2020 Cadence Design Systems.

9 Course Available1 of 2 see next pageTensilica HiFi 5 DSPT ensilica System Modeling using XTSCL earning Map Digital Design and SignoffTensilicaProcessor IP Learning MapTensilica Xtensa NX Processor FundamentalsTensilica Instruction Extension Language and DesignTensilica Xtensa NX Processor InterfacesTensilica XtensaNX Hardware Verification and EDAT ensilica ConnXB10 DSPT ensilica ConnXB20 DSPConnXDSPT ensilica XtensaNX Vision DSP Tensilica Vision Q7 DSPNew Course Number of days for instructor-led course 2020 Cadence Design Systems, Course Available2of 2 see prior pageTensilica System Modeling using XTSC 2020 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and the other Cadence marks found at trademarks or registered trademarks of Cadence Design Systems, Inc. Accellera and SystemC are trademarks of Accellera Systems Initiative Arm products are registered trademarks or trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

10 All MIPI specificationsare registered trademarks or service marks owned by MIPI PCI-SIG specificationsare registered trademarks or trademarks of PCI-SIG. All other trademarks are the property of their respective owners.


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