Memcon: TuningDDR4 for Power Performance - …

1 Tuning DDR4 for Power and PerformanceMike MichelettiProduct Manager Teledyne LeCroyAgenda Introduction DDR4 Technology Expanded role of MRS Power Features Examined Reliability Features Examined Performance Features Examined8/22/20132 DDR4 Goals & Motivations Spec development started in 2005; Officical JEDEC release Aug 2012 Up to Gbps (per pin) 2x Bandwidth Single Ended Signaling Similar clockingEvolutionary Path 8 Bit prefetch, same core frequency Lower Cost 30-40% Power saving (vs DDR3L), tCAL, LP-ASR, Power Savings C/A parity, CRC, MPR readout, ReliabilityAnalysts.

2 50% market penetration by 2015/2016 PowerReliability (RAS)PerformanceSignallingTe s tNew DDR4 Features Categorized4 TCSRTCARCS to CMD Latency (TCAL) VDDQ TermMax Power Saving Page sizeDBI3 DSWrite CRCCA ParityMultipurpose Register (MPR) Readout2133 to 3200 MT/s signalingBank GroupsFine Granularity RefreshSelf Refresh AbortGear Down ModeInternal Vref DQDQ Training with MPRPer DRAM AddressabilityDDR4 Compared to DDR38/22/20135 Spec ItemsDDR3 DDR4 Density / Speed512 Mbp~8Gb ~ ~ ~ (VDD/VDDQ/VPP) ( ) Vref (VDD/2)Internal Vref(Req.)

3 Training)InterfaceData IOCTT (34 ohm)POD(34 ohm)CMD/ADDR IOCTTCTTS trobeBi dir / differential Bi dir / differential# of banks8 banks16 banks(4 BG)CorePage size(x4/8/16)1KB / 1KB / 2KB512B/ 1KB / 2 KBarchitecture# prefetch8 bits8 bitsAdded functionsRESET/ZQ/Dynamic ODT+ CRC/DBI/Multi preamble Physical Package (x4,8/x16)78 / 96 BGA78 / 96 BGADDR4: Command Encoding68/22/2013 Testing DDR4 Protocol Fast, Easy Connection & Setup No Calibration needed Comprehensive Bus Analyzer for ddr3 & DDR4 Traditional Waveform & State Listings Real-Time JEDEC Error Triggering Detects over 65 JEDEC bus & timing violations New Features enabled with MRS.

4 Auto-Self Refresh / Low Power Auto Self Refresh CRC and C/A Parity Error Check Host Tx / Rx Training Pattern Per DRAM addressability (PDA) Internal DQ Vref per DRAM Gear-down mode (for C/C/A) Dynamic ODT CAL mode8/22/2013 Company Confidential8 DDR4 Mode Register Set (MRS) Overview8/22/2013 2013; AMD9 MPR Read Format DLL always EnabledCRC Clear & Parity Error StatusKey Enhancement: DQ Training with MPR DDR4 allows custom patterns for DQ training Host uses MR3 [A2=1] command to initiate DQ Training READ BA[1:0] defines the MPR Location (pattern)8/22/201310 Performance Features: DQ Training Sequence8/22/201311 READ MPR0 (default pattern) Location 0 Back-to-Back Read from MPR is allowed with tCCD=4 nCK for seamless operation8/22/201312 DDR4.

5 Power Features Reduced Voltages ( ) VDDQ Termination (POD) External Vpp Dynamic Bus Inversion (DBI) Page size Temperature controlled Refresh (SR) Low Power Auto-self Refresh (LP ASR) CS to CMD Latency (tCAL) Max Power Saving Mode (MPSM)8/22/201313 Power Features: VDDQ Termination 8/22/2013 2013; Inphi Corporation14 Pseudo Open Drain (POD)Signaling ddr3 utilizes center tap termination DDR4 utilizes VDDQ termination Pseudo open drain signaling Reduces IO current draw DBI: minimize number of zeroes Increase % of bits stored as 1 Improves Performance & Signal integrity Lower Synchronously switching output noisePower Features.

6 External Vpp External Vpp for Word-line Voltage ddr3 utilizes on-die voltage pump to generate higher word line voltage DDR4 utilizes Separate Vpp voltage rail Externally supplied Vpp @ enables more energy efficient memory system Reduces voltage draw & die space8/22/2013 2013; Inphi Corporation15 Command Address Latency (CAL) Command and Address receivers disabled (MR4) CS# used to wakeup the receivers CMD and ADDR sent after a delay of tCAL (latency 3 clocks at )8/22/201316 Power savings: 23% for Idd2n, 10% for Idd0 13% TDP (dual rank DIMM s)Command Address Latency (CAL) Switching Ranks adds CAL Latency CAL mode introduces more latency in multi-threaded IO8/22/201317 Rank 0 Rank 1 Command Address Latency (CAL) CAL mode is better for sequential IO operations Only impacts DRAM when exiting from IDLE 8/22/201318 Rank 0 Rank 1 Power Savings: Server DDR4 vs.

7 ddr3 (Heavy Utilization) 2013; Intel Corporation19 DDR4 results based on Intel projected values for results based on supplier provided Idd values. DDR4: Features Reliability CRC on Writes MPR Error Log Command / Address Parity check8/22/201320 CMD / ADDR Parity Checking When enabled SDRAM verifies parity before executing the command Command and the address lines only Additional delay (parity latency) for tMRD & tMOD (4 to 6 CLKs) PL ranges from 4nCK to 6nCK, depending on clock rate8/22/2013 2013, Samsung Electronics21PL+6ns48 to 96 nCKs @ 2133 CMD / ADDR Parity Error Detection8/22/201322 Controller sees ALERT = LOW for > 48 nCK4 CLKsDDR4: Features Performance Signaling 1066 MHz to (2133 to 3200 MTs) Training - Preamble training.

8 Internal DQ Vref Gear down mode - For speeds above 2666 MT/s CMD/CTR/ADDR sent at 2t Timing Bank Groups8/22/201323 Bank Groups: DDR4 Similar higher data rates So more requests must be kept in-flight to realize higher bandwidth DDR4 supports16 banks divided into 4 bank groups 4 Bank Groups at x4 & x8 2 Bank Groups at x16 8/22/2013 2013; Inphi Corporation24 Separate IO gating structuresallow faster Write-to-Read turnaround between BGBank Group RRD_L, CCD_L, WTR_L ViolationsBank Groups require higher latency between ACTIVATE to same BG1600186621332400 2013.

9 Inphi CorporationtRRD-L Violation Check8/22/201326 Verification Issues: Row Hammer 8/22/201327 A bank of memory is loaded with valid data (green bits) If one row is repeatedly activated (aggressor) in a single refresh cycle, as the charge decays, crosstalk flips a bit in the neighboring rows (victim). REFRESH cannot recover the data. Aggressive row activations can corrupt adjacent rowsRow Usage Report8/22/201328 DDR4 Features: Page sizeTemperature controlled Refresh (SR)Low Power Auto self Refresh (LP ASR)CS to CMD Latency (tCAL)Data Bus Inversion (DBI)Training Bank Groups Gear down mode CRC on Writes Command / Address Parity check8/22/201329 Questions >?

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