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Microelectronics Reliability: Physics-of-Failure Based ...

National Aeronautics and Space Administration Microelectronics reliability : Physics-of-Failure Based Modeling and Lifetime Evaluation Mark White Jet Propulsion Laboratory Pasadena, California Joseph B. Bernstein University of Maryland College Park, Maryland Jet Propulsion Laboratory California Institute of Technology Pasadena, California JPL Publication 08-5 2/08. National Aeronautics and Space Administration Microelectronics reliability : Physics-of-Failure Based Modeling and Lifetime Evaluation NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Assurance Mark White Jet Propulsion Laboratory Pasadena, California Joseph B. Bernstein University of Maryland College Park, Maryland NASA WBS: JPL Project Number: 102197.

Acronyms vi FaRBS Failure Rate Based SPICE FPGA Field Programmable Gate Array FIT Failure in Time FN Fowler-Nordheim GCA Gradual Channel Approximation

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Transcription of Microelectronics Reliability: Physics-of-Failure Based ...

1 National Aeronautics and Space Administration Microelectronics reliability : Physics-of-Failure Based Modeling and Lifetime Evaluation Mark White Jet Propulsion Laboratory Pasadena, California Joseph B. Bernstein University of Maryland College Park, Maryland Jet Propulsion Laboratory California Institute of Technology Pasadena, California JPL Publication 08-5 2/08. National Aeronautics and Space Administration Microelectronics reliability : Physics-of-Failure Based Modeling and Lifetime Evaluation NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Assurance Mark White Jet Propulsion Laboratory Pasadena, California Joseph B. Bernstein University of Maryland College Park, Maryland NASA WBS: JPL Project Number: 102197.

2 Task Number: Jet Propulsion Laboratory 4800 Oak Grove Drive Pasadena, CA 91109. This research was primarily carried out at the University of Maryland under the direction of Professor Joseph B. Bernstein and was sponsored in part by the National Aeronautics and Space Administration Electronic Parts and Packaging (NEPP) Program, the Aerospace Vehicle Systems Institute (AVSI) Consortium specifically, AVSI Project #17: Methods to Account for Accelerated Semiconductor Wearout and the Office of Naval Research. Reference herein to any specific commercial product, process, or service by trade name, trademark, manufacturer, or otherwise, does not constitute or imply its endorsement by the United States Government or the Jet Propulsion Laboratory, California Institute of Technology.

3 Copyright 2008. All rights reserved. ii PREFACE. The solid-state electronics industry faces relentless pressure to improve performance, increase functionality, decrease costs, and reduce design and development time. As a result, device feature sizes are now in the nanometer scale range and design life cycles have decreased to fewer than five years. Until recently, semiconductor device lifetimes could be measured in decades, which was essentially infinite with respect to their required service lives. It was, therefore, not critical to quantify the device lifetimes exactly, or even to understand them completely. For avionics, medical, military, and even telecommunications applications, it was reasonable to assume that all devices would have constant and relatively low failure rates throughout the life of the system; this assumption was built into the design, as well as reliability and safety analysis processes.

4 Technological pressures on the electronics industry to reduce transitor size and decrease cost while increasing transitor count per chip, however, runs counter to the needs of most high- reliability applications where long life with exceptional reliability is critical. As design rules have become tighter, power consumption has increased and voltage margins have become almost non- existent for the designed performance level. In achieving the desired performance levels, the lifetime of most commercial parts is the ultimate casualty. Most large systems are built with the assumption that electronic components will last for decades without failure . However, counter to this assumption, device reliability physics is becoming so well understood that manufacturing foundries are designing microcircuits for a three- to seven-year useful life, as that is what most of the industry seeks.

5 The military, aerospace, medical, and especially the telecommunications industries cannot afford to depend on custom parts for their most sophisticated circuit designs. Hence, we have developed this guideline document as an approach for system designers and device reliability engineers to develop a better understanding of device failures as a result of wearout, and to provide a better understanding of how current reliability models are applied in practice. We describe the best possible approaches to modeling reliability concerns in some of the iii Preface more advanced microelectronic technologies, and provide in-depth descriptions on how to implement into reliability equivalent circuits for spacecraft, planets, instrument, C-matrix, events (SPICE) simulation.

6 Within the inherent limitations of high-power, high-speed, commercial Complementary Metal Oxide Semiconductor (CMOS) devices, suggestions are developed on how to model the incipient failure rate, how to trade circuit performance with reliability , and how to obtain a predictable end-of-life or component-level system repair rate through realistic time- dependent reliability prediction. The development of this handbook for evaluating and simulating microelectronic systems reliability has been an ongoing project of the Microelectronics reliability Engineering program at the University of Maryland, College Park, for more than six years. The program has been funded by the Aerospace Vehicle Systems Institute (AVSI) Consortium and the NASA Electronic Parts and Packaging (NEPP) Program Scaled CMOS reliability Task, as well as the Office of Naval Research.

7 Several doctoral dissertations have resulted from this work and major contributions were carried out by a number of individuals, including J erg Walters, Xiaohu Zhang, Xiaojun Li, Bing Huang, Jin Qin, Mark White, Moshe Gurfinkel, Shahrzad Salami, Qinguo Fan, Zvi Gur, Michael Talmor, and Yoram Shapira. iv ACRONYMS. ADC Analog-to-Digital Converter AHI Anode Hole Injection AHR Anode Hydrogen Release ALT Accelerated Life Testing AST Accelerated Stress Tests ATPG Automatic Test Pattern Generation AVSI Aerospace Vehicle Systems Institute BERT Berkeley reliability Tools BIR Built-In- reliability BTI Biased Temperature Instability CAD Computer Aided Design CADMP-2 Computer-Aided Design of Microelectronic Packages CALCE Computer-Aided Life-Cycle Engineering CDF Cumulative Distribution Function CFR Constant failure Rate CHC Channel Hot Carrier CHE Channel Hot Electron CMOS Complementary Metal Oxide Semiconductor COTS Commercial-off-the-Shelf DAC Digital-to-Analog Converter DAHC Drain Avalanche Hot Carrier DFR Design-For- reliability DNL Differential

8 Nonlinearity EM Electromigration EOS Electrical Overstress ETM Effective Temperature Models v Acronyms FaRBS failure Rate Based SPICE. FPGA Field Programmable Gate Array FIT failure in Time FN Fowler-Nordheim GCA Gradual Channel Approximation GIDL Gate-Induced Drain Leakage GOS Gate Oxide Short HCD Hot Carrier Degradation HCI Hot Carrier Injection HISREM Hot Carrier Induced Series Resistance Enhancement Model HTOL High Temperature Operating Life ICs Integrated Circuits INL Integral Nonlinearity ITRS International Technology Roadmap for Semiconductor KCL Kirchhoff's Current Law LDD Lightly Doped Drain LEM Lucky Electron Model LNA Low Noise Amplifier LSB Least Significant Bit MACRO Maryland Circuit- reliability Oriented MIL-HDBK Military Handbook MOS Metal Oxide Semiconductor MOSFET Metal Oxide Semiconductor Field Effect Transistor MSM Matrix Stressing Method MTBF

9 Mean Time between Failures MTTF Mean-Time-To- failure NBTI Negative Bias Temperature Instability NEPP NASA Electronic Parts and Packaging Program vi Acronyms NMOS N-Channel Metal Oxide Semiconductor NMOSFET N-Channel Metal Oxide Semiconductor Field Effect Transistor PBTI Positive Bias Temperature Instability PMOS P-Channel Metal Oxide Semiconductor PMOSFET P-Channel Metal Oxide Semiconductor Field Effect Transistor PoF Physics-of-Failure RAC reliability Analysis Center RAMP reliability Aware Micro-Processor RF Radio Frequency RT Room Temperature SFDR Spurious-Free-Dynamic-Range SGHE Secondary Generated Hot Electron SHA Sample-and-Hold Amplifier SHE Substrate-Hotelectron S/H Sample-and-Hold SNDR Signal-to-Noise-Plus-Distortion SNM Static Noise Margin SPICE Spacecraft, Planets, Instrument, C-matrix, Events SRAM Static Random Access Memory SoC System-on-Chip SOFR Sum-of- failure - rates TBD Time-to-Breakdown TCAD Technology Computer Aided Design TDDB Time-Dependent Dielectric Breakdown UIUC University of Illinois at Urbana-Champaign VHDL Very High Density Logic VTC Voltage Transfer Characteristics VLSI Very Large Scale Integration vii CONTENTS.

10 Executive Summary ..1. 1 3. Organization .. 3. reliability Prediction from a Historical Perspective .. 4. Traditional 5. Physics-of-Failure Recent Approach: reliability Modeling and Prediction Today ..20. Competing Mechanisms Theory ..23. FaRBS ..24. MaCRO ..25. 2 Electron Device physics of Electromigration ..27. Introduction ..27. Basic physics Process of Statistical Models of EM ..35. Hot Carrier Introduction ..40. Hot Hot Carrier Injection Mechanisms ..42. HCD Models ..45. Acceleration Factors ..52. Time-Dependent Dielectric Breakdown ..52. Introduction ..52. physics of Breakdown ..53. Oxide Breakdown Models ..62. Acceleration Factors ..65. Negative Bias Temperature Instability ..65. Introduction ..65. NBTI failure Mechanisms.


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