N-Channel 30-V (D-S) MOSFET

1 vishay SiliconixSi7636 DPDocument Number: 72768S09-0272-Rev. G, 30-V (D-S) MOSFETFEATURES Halogen-free According to IEC 61249-2-21 Available Ultra-Low On-Resistance Using High Density TrenchFET Gen II Power MOSFET Technology Qg Optimized New Low Thermal Resistance PowerPAK Package with Low mm Profile 100 % Rg Tested APPLICATIONS Low-Side DC/DC Conversion- Notebook- Server- Workstation Synchronous Rectifier, POLPRODUCT SUMMARY VDS (V)RDS(on) ( )ID (A)Qg (Typ.) at VGS = 10 V at VGS = V mm mm PowerP AK SO-8 Bottom ViewOrdering Information: si7636dp -T1-E3 (Lead (Pb)-free) si7636dp -T1-GE3 (Lead (Pb)-free and Halogen-free) N-Channel MOSFETGDSN otes:a. Surface Mounted on 1" x 1" FR4 board.

2 B. See Solder Profile ( ). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposedcopper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed andis not required to ensure adequate bottom side solder Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components. ABSOLUTE MAXIMUM RATINGS TA = 25 C, unless otherwise notedParameter Symbol 10 sSteady State Unit Drain-Source Voltage VDS30 VGate-Source Voltage VGS 20 Continuous Drain Current (TJ = 150 C)aTA = 25 CID2817 ATA = 70 C2213 Pulsed Drain Current (10 s Pulse Width)IDM60 Continuous Source Current (Diode Conduction) CurrentL = mHIAS50 Maximum Power DissipationaTA = 25 = 70 Junction and Storage Temperature Range TJ, Tstg- 55 to 150 CSoldering Recommendations (Peak Temperature)

3 B,c260 THERMAL RESISTANCE RATINGS Parameter Symbol TypicalMaximumUnit Maximum Junction-to-Ambientat 10 sRthJA1924 C/WSteady State5265 Maximum Junction-to-Case (Drain)Steady Number: 72768S09-0272-Rev. G, 16-Feb-09 vishay SiliconixSi7636 DPNotes:a. Pulse test; pulse width 300 s, duty cycle 2 %.b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

4 These are stress ratings only, and functional operationof the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximumrating conditions for extended periods may affect device CHARACTERISTICS 25 C, unless otherwise notedMOSFET SPECIFICATIONS TJ = 25 C, unless otherwise notedParameter Symbol Test Conditions StaticGate Threshold VoltageVGS(th) VDS = VGS, ID = 250 A LeakageIGSSVDS = 0 V, VGS = 20 V 100 nAZero Gate Voltage Drain CurrentIDSSVDS = 30 V, VGS = 0 V 1 AVDS = 30 V, VGS = 0 V, TJ = 55 C 5On-State Drain CurrentaID(on) VDS 5 V, VGS = 10 V 30 ADrain-Source On-State ResistanceaRDS(on)

5 VGS = 10 V, ID = 25 A VGS = V, ID = 19 A Transconductanceagfs VDS = 15 V, ID = 25 A 110 SDiode Forward VoltageaVSDIS = A, VGS = 0 V CapacitanceCissVDS = 15 V, VDS = 0 V, f = 1 MHz5600pFOutput CapacitanceCoss860 Reverse Transfer CapacitanceCrss415 Total Gate ChargeQg VDS = 15 V, VGS = V, ID = 20 A 3650nCGate-Source ChargeQgs 18 Gate-Drain ChargeQgd 10 Gate Tu r n - O n D e l a y T i m etd(on) VDD = 15 V, RL = 15 ID 1 A, VGEN = 10 V, Rg = 6 2435nsRise Timetr1625 Turn-Off Delay Timetd(off) 90140 Fall Timetf3250 Source-Drain Reverse Recovery TimetrrIF = A, dI/dt = 100 A/ s4570 Output Characteristics01020304050600246810 VGS = 10 thru 4 V3 VVDS - Drain-to-Source Voltage (V) - Drain Current (A)IDTransfer Characteristics0 10 20 30 40 50 60 25 C- 55 CVGS - Gate-to-Source Voltage (V)- Drain Current (A)IDT C = 125 CDocument Number: 72768S09-0272-Rev.

6 G, SiliconixSi7636 DPTYPICAL CHARACTERISTICS 25 C, unless otherwise notedOn-Resistance vs. Drain CurrentGate ChargeSource-Drain Diode Forward 01020304050V GS = 10 V - On-Resistance ( )RDS(on)ID - Drain Current (A)V GS = V 0123456051015202530354045 VDS = 15 VID = 20 A- Gate-to-Source Voltage (V) Qg - Total Gate Charge (nC) 10 50 T J = 150 CVSD - Source-to-Drain Voltage (V)- Source Current (A)IS1 TJ = 25 CCapacitanceOn-Resistance vs. Junction TemperatureOn-Resistance vs. Gate-to-Source VoltageCrss01000200030004000500060007000 0612182430 VDS - Drain-to-Source Voltage (V) C - Capacitance (pF) 50- 250255075100 125 150 VGS = 10 V I D = 25 A TJ - Junction Temperature ( C)RDS(on) - On-Resistance(Normalized) 02 46 810ID = 25 A- On-Resistance ( )RDS(on)VGS - Gate-to-Source Voltage (V) Number: 72768S09-0272-Rev.

7 G, 16-Feb-09 vishay SiliconixSi7636 DPTYPICAL CHARACTERISTICS 25 C, unless otherwise notedThreshold Voltage- - - - - - 50 - 25 0 2 5 5 0 7 5 100 125 150 I D = 250 A Variance (V)VGS(th)T J - Temperature ( C)Single Pulse Power, (s)6040 Power (W) Operating Area, 101 TC = 25 CSingle Pulse 10 ms100 by RDS(on)*10 sVDS - Drain-to-Source Voltage (V)* VGS > minimum VGS at which RDS ( on) is specified - Drain Current (A)IDNormalized Thermal Transient Impedance, Junction-to-Ambient10 -3 10 -2 1 1 0 600 10 -1 10 -4 100 2 1 PulseDuty Cycle = Square Wave Pulse Duration (s)Normalized Effective TransientThermal Impedance1.

8 Duty Cycle, D = 2. Per Unit Base = R th J A = 52 C/W3. T JM - TA = PDMZthJA(t)t 1 t 2 t 1 t 2 Notes: 4. Surface Mounted P DM Document Number: 72768S09-0272-Rev. G, SiliconixSi7636 DPTYPICAL CHARACTERISTICS 25 C, unless otherwise notedVishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for SiliconTechnology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, andreliability data, see Thermal Transient Impedance, Junction-to-Case10 -3 10 -2 11010 -1 10 -4 2 1 Pulse Duty Cycle = Square Wave Pulse Duration (s)Normalized Effective TransientThermal ImpedancePackage Siliconix Revison: 13-Feb-171 Document Number: 71655 THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE.

9 THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT SO-8, (Single/Dual) 0 -12 0 -12 : S17-0173-Rev. L, 13-Feb-17 DWG: exclusive of mold flash and cutting will exclusive of mold gate View of Single PadBackside View of Dual PadDetail ZDD1D2c A E1 D1E2D2eb1234H4321 1234bLD2D3 (2x)ZA1K1 KDEWL1D5E3D4E4E4 KLHE2D4D5ME322 vishay SILICONIXP ower MOSFETsApplication Note AN821 PowerPAK SO-8 Mounting and Thermal ConsiderationsAPPLICATION NOTE Revision: 16-Mai-131 Document Number: 71622 For technical questions, contact: DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT Wharton McDanielMOSFETs for switching applications are now available withdie on resistances around 1 m and with the capability tohandle 85 A.

10 While these die capabilities represent a majoradvance over what was available just a few years ago, it isimportant for power MOSFET packaging technology to keeppace. It should be obvious that degradation of a highperformance die by the package is undesirable. PowerPAKis a new package technology that addresses these this application note, PowerPAK s construction isdescribed. Following this mounting information is presentedincluding land patterns and soldering profiles for maximumreliability. Finally, thermal and electrical performance PowerPAK PACKAGEThe PowerPAK package was developed around the SO-8package (figure 1). The PowerPAK SO-8 utilizes the samefootprint and the same pin-outs as the standard SO-8.