NVM ExpressTM Base Specification

1 NVM ExpressTM Revision 1 NVM ExpressTM base Specification NVM express Revision September 21, 2020 Please send comments to NVM ExpressTM Revision 2 NVM ExpressTM base Specification revision is available for download at The NVM express base Specification revision incorporates NVM express base Specification revision , ratified on April 26, 2017 with updated figure references, along with ECN 001, ECN 002, ECN 003, ECN 004a, ECN 005, ECN 006, TP 4000a, TP 4002, TP 4003c, TP 4004b, TP 4005c, TP 4006, TP 4007a, TP 4008, TP 4014, TP 4016, TP 4018b, TP 4022, TP 4024, TP 4025, TP 4027, TP 4028a, TP 4030, TP 4031a, TP 4032, TP 4033, TP 4035, TP 4039a, TP 4042a, TP 4045, TP 4050, TP 4051, TP 4054, and TP 8002 (refer to for details).

2 It also incorporates the NVM express base Specification revision , ratified on June 10, 2019, ECN 001, ECN 002, ECN 003 and ECN 006. Applied the NVM express trademark and logo usage guidelines. Specification DISCLAIMER LEGAL NOTICE: Copyright 2007 to 2020 NVM express , Inc. ALL RIGHTS RESERVED. This NVM express base Specification revision is proprietary to the NVM express , Inc. (also referred to as Company ) and/or its successors and assigns. NOTICE TO USERS WHO ARE NVM express , INC. MEMBERS: Members of NVM express , Inc. have the right to use and implement this NVM express base Specification revision subject, however, to the Member s continued compliance with the Company s Intellectual Property Policy and Bylaws and the Member s Participation Agreement.

3 NOTICE TO NON-MEMBERS OF NVM express , INC.: If you are not a Member of NVM express , Inc. and you have obtained a copy of this document, you only have a right to review this document or make reference to or cite this document. Any such references or citations to this document must acknowledge NVM express , Inc. copyright ownership of this document. The proper copyright citation or reference is as follows: 2007 to 2020 NVM express , Inc. ALL RIGHTS RESERVED. When making any such citations or references to this document you are not permitted to revise, alter, modify, make any derivatives of, or otherwise amend the referenced portion of this document in any way without the prior express written permission of NVM express , Inc.

4 Nothing contained in this document shall be deemed as granting you any kind of license to implement or use this document or the Specification described therein, or any of its contents, either expressly or impliedly, or to any intellectual property owned or controlled by NVM express , Inc., including, without limitation, any trademarks of NVM express , Inc. LEGAL DISCLAIMER: THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN IS PROVIDED ON AN AS IS BASIS. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, NVM express , INC. (ALONG WITH THE CONTRIBUTORS TO THIS DOCUMENT) HEREBY DISCLAIM ALL REPRESENTATIONS, WARRANTIES AND/OR COVENANTS, EITHER express OR IMPLIED, STATUTORY OR AT COMMON LAW, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, VALIDITY, AND/OR NONINFRINGEMENT.

5 All product names, trademarks, registered trademarks, and/or servicemarks may be claimed as the property of their respective owners. The NVM express design mark is a registered trademark of NVM express , Inc. PCI-SIG and PCIe are registered trademarks of PCI-SIG. NVM express Workgroup c/o VTM, Inc. 3855 SW 153rd Drive Beaverton, OR 97003 USA NVM ExpressTM Revision 3 Table of Contents 1 INTRODUCTION .. 6 Overview .. 6 Scope .. 6 Outside of Scope .. 6 Theory of Operation .. 7 Conventions .. 12 Definitions .. 13 Keywords .. 18 Byte, Word, and Dword Relationships .. 19 References .. 19 References Under Development.

6 20 2 SYSTEM BUS (PCI express ) REGISTERS .. 21 PCI Header .. 21 PCI Power Management Capabilities .. 26 Message Signaled Interrupt Capability (Optional) .. 28 MSI-X Capability (Optional) .. 29 PCI express Capability .. 31 Advanced Error Reporting Capability (Optional) .. 36 Other Capability Pointers .. 41 3 CONTROLLER REGISTERS .. 42 Register Definition .. 42 Index/Data Pair registers (Optional) .. 61 4 DATA STRUCTURES .. 63 Submission Queue & Completion Queue 63 Submission Queue Entry Command Format .. 65 Physical Region Page Entry and List .. 69 Scatter Gather List (SGL) .. 70 Metadata Region (MR) .. 76 Completion Queue 77 Controller Memory Buffer.

7 85 Persistent Memory Region .. 86 NVM Sets .. 88 Namespace List .. 89 Controller List .. 90 Fused Operations .. 90 Command Arbitration .. 91 5 ADMIN COMMAND SET .. 94 Abort command .. 95 Asynchronous Event Request command .. 96 Create I/O Completion Queue command .. 101 Create I/O Submission Queue command .. 102 Delete I/O Completion Queue command .. 104 Delete I/O Submission Queue command .. 105 Doorbell Buffer Config command .. 106 Device Self-test command .. 107 Directive Receive command .. 109 Directive Send command .. 110 Firmware Commit command .. 110 NVM ExpressTM Revision 4 Firmware Image Download command.

8 112 Get Features command .. 113 Get Log Page command .. 116 Identify command .. 161 Keep Alive command .. 201 NVMe-MI Receive command .. 201 NVMe-MI Send command .. 201 Namespace Attachment command .. 201 Namespace Management 202 Set Features command .. 205 Virtualization Management command .. 232 Format NVM command NVM Command Set Specific .. 234 Sanitize command NVM Command Set Specific .. 236 Security Receive command NVM Command Set Specific .. 240 Security Send command NVM Command Set Specific .. 241 Get LBA Status command NVM Command Set 242 6 NVM COMMAND SET .. 246 Namespaces .. 247 Fused Operations.

9 250 Command Ordering Requirements .. 250 Atomic Operations .. 251 End-to-end Protection Information .. 254 Compare command .. 255 Dataset Management command .. 257 Flush command .. 260 Read command .. 260 Reservation Acquire command .. 263 Reservation Register command .. 264 Reservation Release command .. 265 Reservation Report command .. 266 Verify command .. 269 Write command .. 270 Write Uncorrectable command .. 273 Write Zeroes command .. 274 7 CONTROLLER ARCHITECTURE .. 276 Introduction .. 276 Command Submission and Completion Mechanism (Informative) .. 285 Resets .. 292 Queue Management .. 293 Interrupts.

10 294 Controller Initialization and Shutdown Processing .. 297 Asynchronous Event Request Host Software Recommendations (Informative) .. 299 Feature Values .. 300 NVMe Qualified Names .. 301 Identifier Format and Layout (Informative) .. 302 Unique Identifier .. 305 Keep Alive .. 306 Updating Controller Doorbell Registers using a Shadow Doorbell Buffer .. 308 Privileged Actions .. 309 8 FEATURES .. 310 Firmware Update Process .. 310 Metadata Handling .. 311 NVM ExpressTM Revision End-to-end Data Protection (Optional) .. 312 Power Management .. 318 Virtualization Enhancements (Optional) .. 323 Doorbell Stride for Software Emulation.