Transcription of PCI Express Base Specification Revision 2
1 PCI Express base Specification Revision December 20, 2006 2 Revision Revision History DATE Initial release. 07/22/02 Incorporated Errata C1-C66 and 04/15/03 Incorporated approved Errata and ECNs. 03/28/05 Added GT/s data rate and incorporated approved Errata and ECNs. 12/20/06 PCI-SIG disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does PCI-SIG make a commitment to update the information contained herein. Contact the PCI-SIG office to obtain the latest Revision of this Specification . Questions regarding the PCI Express base Specification or membership in PCI-SIG may be forwarded to: Membership Services E-mail: Phone: 503-619-0569 Fax: 503-644-6708 Technical Support DISCLAIMER This PCI Express base Specification is provided as is with no warranties whatsoever, including any warranty of merchantability, noninfringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, Specification , or sample.
2 PCI-SIG disclaims all liability for infringement of proprietary rights, relating to use of information in this Specification . No license, Express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. PCI, PCI Express , PCIe, and PCI-SIG are trademarks or registered trademarks of PCI-SIG. All other product names are trademarks, registered trademarks, or servicemarks of their respective owners. Copyright 2002-2006 PCI-SIG PCI Express base Specification , REV. 3 Contents OBJECTIVE OF THE 21 DOCUMENT ORGANIZATION .. 21 DOCUMENTATION CONVENTIONS .. 22 TERMS AND ACRONYMS .. 23 REFERENCE 29 1. INTRODUCTION ..31 A THIRD GENERATION I/O 31 PCI Express 33 PCI Express FABRIC 35 Root 35 Endpoints .. 36 Switch .. 39 Root Complex Event 40 PCI Express to PCI/PCI-X 40 PCI Express FABRIC TOPOLOGY 40 PCI Express LAYERING 41 Transaction Layer.
3 42 Data Link Layer .. 42 Physical Layer .. 43 Layer Functions and Services .. 43 2. TRANSACTION LAYER Specification .. 47 TRANSACTION LAYER 47 Address Spaces, Transaction Types, and 48 Packet Format Overview .. 50 TRANSACTION LAYER PROTOCOL - PACKET 51 Common Packet Header Fields .. 51 TLPs with Data Payloads - Rules .. 54 TLP Digest Rules .. 56 Routing and Addressing Rules .. 56 First/Last DW Byte Enables 59 Transaction Descriptor .. 61 Memory, I/O, and Configuration Request 66 Message Request Rules .. 69 Completion Rules .. 80 HANDLING OF RECEIVED 82 Request Handling Rules .. 85 PCI Express base Specification , REV. 4 Completion Handling Rules .. 98 TRANSACTION 100 Transaction Ordering Rules .. 100 Update Ordering and Granularity Observed by a Read Transaction.
4 104 Update Ordering and Granularity Provided by a Write Transaction .. 105 VIRTUAL CHANNEL (VC) 105 Virtual Channel Identification (VC ID) .. 108 TC to VC Mapping .. 109 VC and TC 110 ORDERING AND RECEIVE BUFFER FLOW 111 Flow Control Rules .. 112 DATA 122 ECRC Rules .. 123 Error Forwarding .. 127 COMPLETION TIMEOUT 129 LINK STATUS 130 Transaction Layer Behavior in DL_Down 130 Transaction Layer Behavior in DL_Up Status .. 131 3. DATA LINK LAYER Specification .. 133 DATA LINK LAYER 133 DATA LINK CONTROL AND MANAGEMENT STATE 135 Data Link Control and Management State Machine Rules .. 136 FLOW CONTROL INITIALIZATION 138 Flow Control Initialization State Machine Rules .. 138 DATA LINK LAYER PACKETS (DLLPS) .. 142 Data Link Layer Packet Rules.
5 142 DATA 147 147 LCRC, Sequence Number, and Retry Management (TLP Transmitter).. 147 LCRC and Sequence Number (TLP Receiver) .. 159 4. PHYSICAL LAYER Specification .. 167 167 LOGICAL 167 Symbol Encoding .. 168 Framing and Application of Symbols to 171 Data Scrambling .. 174 Link Initialization and 176 Link Training and Status State Machine (LTSSM) 188 Link Training and Status State 192 Clock Tolerance Compensation .. 237 Compliance Pattern .. 239 Modified Compliance 240 ELECTRICAL 241 Maintaining Backwards Compatibility .. 241 Jitter Budgeting and Measurement .. 243 PCI Express base Specification , REV. 5 Transmitter 244 Receiver 259 Transmitter and Receiver DC 273 Channel 278 Reference Clock 285 5. POWER 293 293 Statement of 294 LINK STATE POWER 294 PCI-PM SOFTWARE COMPATIBLE 299 Device Power Management States (D-States) of a 299 PM Software Control of the Link Power Management 303 Power Management Event Mechanisms.
6 308 NATIVE PCI Express POWER MANAGEMENT 315 Active State Power Management (ASPM) .. 315 AUXILIARY POWER 331 Auxiliary Power 331 POWER MANAGEMENT SYSTEM MESSAGES AND 332 6. SYSTEM ARCHITECTURE .. 335 INTERRUPT AND PME 335 Rationale for PCI Express Interrupt 335 PCI Compatible INTx 336 INTx Emulation Software Model .. 336 Message Signaled Interrupt (MSI/MSI-X) 336 PME 338 Native PME Software Model .. 338 Legacy PME Software Model .. 339 Operating System Power Management 339 PME Routing Between PCI Express and PCI Hierarchies .. 339 ERROR SIGNALING AND 340 Scope .. 340 Error Classification .. 340 Error Signaling .. 342 Error Logging .. 349 Sequence of Device Error Signaling and Logging Operations .. 352 Error Message Controls.
7 354 Error Listing and Rules .. 355 Virtual PCI Bridge Error 359 VIRTUAL CHANNEL 360 Introduction and Scope .. 360 TC/VC Mapping and Example 361 VC Arbitration .. 363 Isochronous Support .. 371 DEVICE 374 LOCKED 375 PCI Express base Specification , REV. 6 375 Initiation and Propagation of Locked Transactions - 376 Switches and Lock - 377 PCI Express /PCI Bridges and Lock - Rules .. 377 Root Complex and Lock - 378 Legacy 378 PCI Express Endpoints .. 378 PCI Express RESET - 378 Conventional Reset .. 378 Function-Level Reset (FLR).. 381 PCI Express HOT-PLUG 384 Elements of Hot-Plug .. 385 Registers Grouped by Hot-Plug Element Association .. 391 PCI Express Hot-Plug Events .. 393 Firmware Support for Hot-Plug .. 396 POWER BUDGETING 396 System Power Budgeting Process 397 SLOT POWER LIMIT 397 ROOT COMPLEX TOPOLOGY 400 LINK SPEED 402 ACCESS CONTROL SERVICES (ACS).
8 403 ACS Component Capability Requirements .. 404 Interoperability .. 408 ACS Peer-to-Peer Control 408 ACS Violation Error Handling .. 409 ACS Redirection Impacts on Ordering Rules .. 410 7. SOFTWARE INITIALIZATION AND 413 CONFIGURATION 413 PCI Express CONFIGURATION 414 PCI Compatible Configuration Mechanism .. 415 PCI Express Enhanced Configuration Access Mechanism (ECAM) .. 416 Root Complex Register Block .. 420 CONFIGURATION TRANSACTION 421 Device 421 Configuration Transaction 422 Configuration Request Routing 422 PCI Special 423 CONFIGURATION REGISTER 424 PCI-COMPATIBLE CONFIGURATION 425 Type 0/1 Common Configuration Space .. 426 Type 0 Configuration Space 432 Type 1 Configuration Space 434 PCI POWER MANAGEMENT CAPABILITY 438 MSI AND MSI-X CAPABILITY 439 PCI Express CAPABILITY 440 PCI Express Capability List Register (Offset 00h).
9 441 PCI Express base Specification , REV. 7 PCI Express Capabilities Register (Offset 02h) .. 442 Device Capabilities Register (Offset 04h) .. 444 Device Control Register (Offset 08h) .. 449 Device Status Register (Offset 0Ah).. 455 Link Capabilities Register (Offset 0Ch).. 458 Link Control Register (Offset 10h) .. 462 Link Status Register (Offset 12h) .. 469 Slot Capabilities Register (Offset 14h) .. 472 Slot Control Register (Offset 18h) .. 474 Slot Status Register (Offset 1Ah).. 478 Root Control Register (Offset 1Ch) .. 480 Root Capabilities Register (Offset 1Eh) .. 482 Root Status Register (Offset 20h).. 482 Device Capabilities 2 Register (Offset 24h) .. 483 Device Control 2 Register (Offset 28h) .. 485 Device Status 2 Register (Offset 2Ah).. 487 Link Capabilities 2 Register (Offset 2Ch).
10 487 Link Control 2 Register (Offset 30h) .. 487 Link Status 2 Register (Offset 32h) .. 492 Slot Capabilities 2 Register (Offset 34h) .. 492 Slot Control 2 Register (Offset 38h) .. 492 Slot Status 2 Register (Offset 3Ah).. 492 PCI Express EXTENDED 493 Extended Capabilities in Configuration 493 Extended Capabilities in the Root Complex Register Block .. 493 PCI Express Enhanced Capability 494 ADVANCED ERROR REPORTING 495 Advanced Error Reporting Enhanced Capability Header (Offset 00h).. 496 Uncorrectable Error Status Register (Offset 04h).. 497 Uncorrectable Error Mask Register (Offset 08h) .. 498 Uncorrectable Error Severity Register (Offset 0Ch) .. 499 Correctable Error Status Register (Offset 10h).. 501 Correctable Error Mask Register (Offset 14h) .. 502 Advanced Error Capabilities and Control Register (Offset 18h).
