Pass-Transistor Logic

1 Pass-Transistor Logic 1. EE141. Pass-Transistor Logic B. Switch Out A. Out Inputs Network B. B. N transistors No static consumption Primary inputs drive the gate terminals + source-drain terminals. In contrast to static CMOS . primary inputs drive gate terminals. 2. EE141. Example: AND Gate When B is 1 , top device turns on and copies the input B. A to output F. When B is low, bottom device turns on and passes a 0 . A. The presence of the switch driven by B is essential to ensure that the gate is static a low-impedance path B. must exist to supply rails. F = AB. Adv.: Fewer devices to implement some functions. Example: AND2 requires 4 devices (including inverter to 0. invert B) vs. 6 for complementary CMOS (lower total capacitance). NMOS is effective at passing a 0, but poor at pulling a node to Vdd.

2 When the pass transistor a node high, the output only charges up to Vdd-Vtn. This becomes worse due to the body effect. The node will be charged up to Vdd Vtn (Vs). Vs = Vdd (Vtn0 + ( 2 f + Vs 2 f )). 3. EE141. NMOS-Only Logic In In m VDD s Out Voltage [V]. Out s m m 0 1 2. Time [ns]. Vs is initially 0. Vs will initially charge up quickly, but the tail end of the transient is slow. The current drive of the transistor (gate-to-source voltage) is reduce significantly as Vs approaches Vdd-Vtn (the current available to charge up node s is reduced drastically. For cascading, the output of a pass transistor (#1) should not drive the gate of another MOS. device (#2). This will produce an output = Vdd-Vtn1-Vtn2. 4. EE141. Energy Consumption In m VDD s Out m m pass transistors require lower switching energy to charge up a node, due to the reduces voltage swing.)

3 The output node charges from 0 -> Vdd-Vtn, and the energy drawn from the power supply for charging the output of a pass transistor is given by (Vdd-Vtn ). While lower switching power is consumed, it may consume static power when output is high . the reduced voltage level may be insufficient to turn off the PMOS transistor of the subsequent CMOS inverter. 5. EE141. Complementary pass transistor Logic A. Pass-Transistor A F. B Network B To accept and produce true (a) and complementary inputs A Inverse and outputs. A Pass-Transistor F. B. B Network B B B B B B. A A A. B F=AB B F=A+B A F=A . A A A (b). B F = AB B F =A+B A F = A . AND/NAND OR/NOR EXOR/NEXOR. Since circuit is differential, complimentary inputs and outputs are available. Although generating differential signals require extra circuitry, complex gates such as XORs, MUXs and adders can be realized efficiently.

4 CPL is a static gate, because outputs are connected to Vdd or GND through a low-resistance path (high noise resilience). Design is modular all gates use same topology; only inputs are permuted. This facilitates the design of a library of gates. 6. EE141. Main Problems of NMOS-only Switch C = C = V. M2. A = V A = V B. Mn B. CL M1. VB does not pull up to , but - VTN. Threshold voltage loss causes static power consumption + slower transition 7. EE141. NMOS Only Logic : Level Restoring transistor VDD. VDD. Level Restorer Mr B. M2. X. A Mn Out M1. Advantage: Full Swing. Eliminates static power in inverter + static power through level restorer and pass transistor , since restorer is only active when A is high. Restorer adds capacitance, takes away pull down current at X contention between Mn and Mr (slower switching).

5 Hence Mr must be sized small. Mn and Mr must be sized such that the voltage at node X drops below the threshold of the inverter VM, which is a function in the sizes of M1 and M2. 8. EE141. Solution 2: Single transistor pass Gate with VT~0. V DD. Use very low threshold values for NMOS. pass transistors, and standard high- VDD. threshold devices for inverters. 0V Note: Body effect will still cause an increase in the threshold voltage. VDD 0V Out WATCH OUT FOR LEAKAGE CURRENTS. (DC Sneak path). While these leakage paths are not critical when the device is switching constantly, they do pose a large energy overhead when the circuit is in the ideal state. 9. EE141. Solution 3: Transmission Gate C. C. NMOS passes a strong 0 . A B A B. PMOS passes a strong 1 . Transmission gates enable rail-to-rail swing C.

6 C. These gates are particularly efficient in implementing MUXs C = V. S. VDD A = V. B. A. CL. M2. C= 0 V. S F. M1. B. S. F=(AS+ BS) 6 devices vs. 8 for complementary CMOS 10. EE141. Another Example: Transmission Gate XOR. 6 devices (including inverter for B) vs. 12 for complementary CMOS B. For B=1, M3 & M4 are off, M1 & M2 are on. F = AB. B. For B=0, M1 & M2 are off. M3 & M4 are on. F = AB M2. Regardless of the value of A & B, node F is A A. connected to Vdd or GND (static gate) F. M1 M3/M4. B. B. 11. EE141. Resistance of Transmission Gate 30. V. Rn Rn Resistance, ohms 20 Rp V Vout Rp 0V. 10. R n || Rp 0. Vout, V. Rn {(Vdd-Vout)/In} & Rp {(Vdd-Vout)/Ip} are in parallel. The currents through devices are dependent on value of Vout and hence the operating mode of the transistors. During the low- to-high transition, the pass transistors traverse through a number of operation modes.

7 Since Vd and Vg = Vdd, the NMOS is either in saturation or off. The PMOS changes from saturation to linear during the transient. 12. EE141. 30. V. Rn Rn Resistance, oh ms 20 Rp V Vout Rp 0 V. 10. Rn || R p 0. Vout , V. q Vout < |Vtp|: NMOS and PMOS saturated q |Vtp| < Vout < Vdd Vtn: NMOS saturated, PMOS linear q Vdd -Vtn < Vout: NMOS cutoff, PMOS linear Req is relatively constant. Thus when analyzing transmission-gate networks, the simplifying assumption that the switch has a constant resistive value is acceptable. Vdd Vout Vdd Vout 1. Rn = = . In (Vdd Vout ) 2 k n (Vdd Vtn ). k n (Vdd Vtn )(Vdd Vout ) . 2 . Similarly, V V 1. Rp = dd out . Ip k p (Vdd Vtp ) 13. EE141. Delay in Transmission Gate Networks V1 Vi-1 Vi Vi+1 Vn-1 Vn In C C C C C. 0 0 0 0. (a). Req Req Req Req V1 Vi Vi+1 Vn-1 Vn In C C C C C.

8 (b). n n( n + 1). t p = CReq k = k =0 2. tp is proportional to n 2 and increases rapidly with the number of switches in the chain. Solution: Insert buffers. 14. EE141. Delay Optimization V1 Vi-1 Vi Vi+1 Vn-1 Vn In C C C C C. 0 0 0 0. (a). Req Req Req Req V1 Vi Vi+1 Vn-1 Vn In C C C C C. (b). m Req Req Req Req Req Req In C CC C C CC C. (c). n m( m + 1) n . t p = CReq + 1 tbuf Linear dependence on n instead of n2. m 2 m . t p t buf To find mopt, then = 0 yielding mopt = 15. EE141. m CReq