PCI Local Bus Specification

1 PCI Local BusSpecificationRevision 18, 1998 Revision issue6/22 connector and expansion board specification4/30 clarifications and added 66 MHz chapter6/1 ECNs and improved readability12/18/987KH 3&, 6 SHFLDO ,QWHUHVW *URXS GLVFODLPV DOO ZDUUDQWLHV DQG OLDELOLW\ IRU WKH XVH RI WKLV GRFXPHQWDQG WKH LQIRUPDWLRQ FRQWDLQHG KHUHLQ DQG DVVXPHV QR UHVSRQVLELOLW\ IRU DQ\ HUURUV WKDW PD\ DSSHDULQ WKLV GRFXPHQW QRU GRHV WKH 3&, 6 SHFLDO ,QWHUHVW *URXS PDNH D FRPPLWPHQW WR XSGDWH WKHLQIRUPDWLRQ FRQWDLQHG KHUHLQ &RQWDFW WKH 3&, 6 SHFLDO ,QWHUHVW *URXS RIILFH WR REWDLQ WKH ODWHVW UHYLVLRQ RI WKH VSHFLILFDWLRQ 4 XHVWLRQV UHJDUGLQJ WKH 3&, VSHFLILFDWLRQ RU PHPEHUVKLS LQ WKH 3&, 6 SHFLDO ,QWHUHVW *URXS PD\ EHIRUZDUGHG WR 3&, 6 SHFLDO ,QWHUHVW *URXS 1 ( .DWKU\Q +LOOVERUR 2 UHJRQ 3 KRQH ,QVLGH WKH 8 6 2 XWVLGH WKH 8 6 )D[ H PDLO SFLVLJ#SFLVLJ ',6&/$,0(57 KLV 3&, /RFDO %XV 6 SHFLILFDWLRQ LV SURYLGHG DV LV ZLWK QR ZDUUDQWLHV ZKDWVRHYHU LQFOXGLQJ DQ\ ZDUUDQW\ RI PHUFKDQWDELOLW\ QRQLQIULQJHPHQW ILWQHVV IRU DQ\ SDUWLFXODUSXUSRVH RU DQ\ ZDUUDQW\ RWKHUZLVH DULVLQJ RXW RI DQ\ SURSRVDO VSHFLILFDWLRQ RU VDPSOH 7KH 3&, 6,* GLVFODLPV DOO OLDELOLW\ IRU LQIULQJHPHQW RI SURSULHWDU\ ULJKWV UHODWLQJ WR XVHRI LQIRUPDWLRQ LQ WKLV VSHFLILFDWLRQ 1R OLFHQVH H[SUHVV RU LPSOLHG E\ HVWRSSHO RURWKHUZLVH WR DQ\ LQWHOOHFWXDO SURSHUW\ ULJKWV LV JUDQWHG KHUHLQ $/3+$ LV D UHJLVWHUHG WUDGHPDUN RI 'LJLWDO (TXLSPHQW &RUSRUDWLRQ )LUH:LUH LV D WUDGHPDUN RI $SSOH &RPSXWHU ,QF 7 RNHQ 5 LQJ DQG 9*$ DUH WUDGHPDUNV DQG 36 ,%0 0 LFUR &KDQQHO 26 DQG 3& $7 DUH UHJLVWHUHGWUDGHPDUNV RI ,%0 &RUSRUDWLRQ.)]]

2 LQGRZV 06 '26 DQG 0 LFURVRIW DUH UHJLVWHUHG WUDGHPDUNV RI 0 LFURVRIW &RUSRUDWLRQ 7 ULVWDWH LV D UHJLVWHUHG WUDGHPDUN RI 1 DWLRQDO 6 HPLFRQGXFWRU 1X%XV LV D WUDGHPDUN RI 7H[DV ,QVWUXPHQWV (WKHUQHW LV D UHJLVWHUHG WUDGHPDUN RI ;HUR[ &RUSRUDWLRQ $OO RWKHU SURGXFW QDPHV DUH WUDGHPDUNV UHJLVWHUHG WUDGHPDUNV RU VHUYLFHPDUNV RI WKHLU UHVSHFWLYH RZQHUV Copyright 1992, 1993, 1995, 1998 PCI Special Interest GroupRevision 1 Specification Contents .. Motivation .. PCI Local Bus Applications .. PCI Local Bus Overview .. PCI Local Bus Features and Benefits .. Administration .. 6 Chapter 2 Signal Signal Type Definition .. Pin Functional Groups .. System Pins .. Address and Data Pins .. Interface Control Pins .. Arbitration Pins (Bus Masters Only) .. Error Reporting Pins .. Interrupt Pins (Optional) .. Additional Signals.)]]

3 64-Bit Bus Extension Pins (Optional) .. JTAG/Boundary Scan Pins (Optional) .. Sideband Signals .. Central Resource 19 Revision 3 Bus Bus Command Definition .. Command Usage Rules .. PCI Protocol Fundamentals .. Basic Transfer Control .. Addressing .. I/O Space Decoding .. Memory Space Decoding .. Configuration Space Byte Lane and Byte Enable Usage .. Bus Driving and Turnaround .. Transaction Ordering and Posting .. Transaction Ordering and Posting for Simple Devices .. Transaction Ordering and Posting for Bridges .. Combining, Merging, and Collapsing .. Bus Transactions .. Read Transaction .. Write Transaction .. Transaction Termination .. Master Initiated Termination .. Target Initiated Termination .. Delayed Transactions .. Arbitration .. Arbitration Signaling Protocol.

4 Fast Back-to-Back Transactions .. Arbitration Parking .. Latency .. Target Latency .. Target Initial Latency .. Target Subsequent Latency .. 77 Revision Master Data Memory Write Maximum Completion Time Limit .. Arbitration Latency .. Bandwidth and Latency Considerations .. Determining Arbitration Latency .. Determining Buffer Requirements .. Other Bus Operations .. Device Selection .. Special Cycle .. Address/Data Stepping .. Interrupt Acknowledge .. Error Functions .. Parity Generation .. Parity Checking .. Address Parity Errors .. Error Data Parity Error Signaling on PERR# .. Other Error Signaling on SERR# .. Master Data Parity Error Status Bit .. Detected Parity Error Status Bit .. Delayed Transactions and Data Parity Errors .. Error Recovery .. 64-Bit Bus Determining Bus Width During System Initialization.

5 64-bit Addressing .. Special Design Considerations .. 108 Revision 4 Electrical Overview .. 5V to Transition Road Map .. Dynamic vs. Static Drive Specification .. Component Specification .. 5V Signaling Environment .. DC Specifications .. AC Specifications .. Maximum AC Ratings and Device Protection .. Signaling Environment .. DC Specifications .. AC Specifications .. Maximum AC Ratings and Device Protection .. Timing Specification .. Clock Specification .. Timing Measurement and Test Conditions .. Indeterminate Inputs and Metastability .. Vendor Provided Pinout Recommendation .. System (Motherboard) Clock Reset .. Pull-ups .. Power .. Power Requirements .. System Timing Budget .. Physical Requirements .. Routing and Layout Recommendations for Four-Layer Motherboards.

6 Motherboard Impedance .. 141 Revision Connector Pin Assignments .. Expansion Board Specification .. Board Pin Assignment .. Power Power Consumption .. Physical Requirements .. Trace Length Limits .. Routing Recommendations for Four-Layer Expansion Boards .. Signal 5 Mechanical Overview .. Expansion Card Physical Dimensions and Tolerances .. Connector Physical Description .. Connector Physical Connector Performance Specification .. Planar Implementation .. 178 Chapter 6 Configuration Configuration Space Organization .. Configuration Space Functions .. Device Identification .. Device Device Status .. Miscellaneous Registers .. Base Addresses .. Address Maps .. Expansion ROM Base Address Register .. PCI Expansion ROMs .. PCI Expansion ROM 206 Revision PCI Expansion ROM Header Format.

7 PCI Data Structure Format .. Power-on Self Test (POST) Code .. PC-compatible Expansion ROM Header Extensions .. Vital Product Data .. Device Drivers .. System Reset .. Capabilities List .. Message Signaled Interrupts .. Message Capability Structure .. Capability ID .. Next Pointer .. Message Control .. Message Address .. Message Upper Address (Optional) .. Message MSI Operation .. MSI Transaction Termination .. MSI Transaction Reception and Ordering Requirements .. 220 Chapter 7 66 Mhz PCI Introduction .. Scope .. Device Implementation Considerations .. Configuration Space .. Agent Architecture .. 66 MHZ_ENABLE (M66EN) Pin Definition .. Latency .. 223 Revision Electrical Overview .. Transition Roadmap to 66 MHz PCI .. Signaling Environment.

8 DC Specifications .. AC Specifications .. Maximum AC Ratings and Device Protection .. Timing Specification .. Clock Specification .. Timing Measurement and Test Conditions .. Vendor Provided Specification .. Recommendations .. Pinout Recommendations .. Clocking System (Planar) Specification .. Clock Reset .. Pullups .. Power .. Power System Timing Budget .. Physical Requirements .. Routing and Layout Recommendations for Four-Layer Boards .. Planar Impedance .. Connector Pin Assignments .. Expansion Board Specifications .. 237 Revision A Special Cycle Messages ..239 Appendix B State Machines ..241 Appendix C Operating D Class E System Transaction F Exclusive G I/O Space Address Decoding for Legacy Devices.

9 285 Appendix H Capability I Vital Product Data ..289 Glossary ..297 Revision 1-1: PCI Local Bus Applications .. 2 Figure 1-2: PCI System Block 3 Figure 2-1: PCI Pin List .. 7 Figure 3-1: Address Phase Formats of Configuration Transactions .. 31 Figure 3-2: Layout of CONFIG_ADDRESS Register .. 32 Figure 3-3: Host Bridge Translation for Type 0 Configuration Transactions Address 33 Figure 3-4: Configuration Read .. 38 Figure 3-5: Basic Read Operation .. 47 Figure 3-6: Basic Write Operation .. 48 Figure 3-7: Master Initiated Termination .. 50 Figure 3-8: Master-Abort Termination .. 51 Figure 3-9: Retry .. 55 Figure 3-10: Disconnect With 56 Figure 3-11: Master Completion Termination .. 57 Figure 3-12: Disconnect-1 Without Data Termination .. 58 Figure 3-13: Disconnect-2 Without Data Termination .. 58 Figure 3-14: Target-Abort.

10 59 Figure 3-15: Basic Arbitration ..70 Figure 3-16: Arbitration for Back-to-Back Access .. 74 Figure 3-17: DEVSEL# Assertion .. 89 Figure 3-18: Address Stepping ..92 Figure 3-19: Interrupt Acknowledge 93 Figure 3-20: Parity 94 Figure 3-21: 64-bit Read Request With 64-bit Transfer .. 103 Figure 3-22: 64-bit Write Request With 32-bit Transfer .. 104 Revision 3-23. 64-Bit Dual Address Read 107 Figure 4-1: PCI Board Connectors .. 114 Figure 4-2: V/I Curves for 5V 120 Figure 4-3: Maximum AC Waveforms for 5V Signaling .. 121 Figure 4-4: V/I Curves for 124 Figure 4-5: Maximum AC Waveforms for Signaling .. 125 Figure 4-6: Clock Waveforms .. 126 Figure 4-7: Output Timing Measurement Conditions .. 129 Figure 4-8: Input Timing Measurement Conditions .. 129 Figure 4-9: Suggested Pinout for PQFP PCI Component .. 132 Figure 4-10: Clock Skew Diagram.