Enhanced Serial Peripheral Interface (eSPI)

1 327432-002 Enhanced Serial Peripheral Interface (eSPI) Interface Base specification (for Client and Server Platforms) January 2016 Revision 2 327432-004 Inte l he reby grants yo u a fully-paid, non-exclusive, non-transferable, w orldwide, limited license (w ithout the right to sublicense), under its copyrights to view, download, and reproduce the Enhanced Serial Peripheral Interface (eSPI) specification (" specification "). You are not granted any other rights or licenses, by implication, estoppel, or otherwise, and you may not create any derivative w orks of the specification . The specification is provided "as is," and intel makes no representations or w arranties, express or implied, including warranties of merchantability, fitness for a particular purpose, non-infringement, or title.

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6 All Rights Reserved * Other names and brands may be claimed as the property of others. Copyright 2016, intel Corporation. All rights reserved. 327432-004 3 Contents 1 8 2 Introduct ion .. 9 Requirements .. 12 3 Architecture Overview .. 14 System Topology .. 14 Architecture Descriptions .. 18 Pin Descript ions .. 22 4 Bus Protocol .. 24 Basic Protocol .. 24 Command Phase .. 28 Turn-Around (TAR) .. 33 Response Phase .. 34 Response .. 34 Status .. 36 Ale rt Phase .. 39 Get Status 42 Get Configurat ion and Set Configurat ion Command .. 43 Non-Posted Transaction .. 44 Posted Transaction .. 49 WAIT STATE .. 51 5 Transaction Layer.

7 53 Cycle Types and Packet 53 Cycle 54 Tag .. 57 Length .. 57 58 59 Channels .. 59 Peripheral Channel .. 59 Virtual Wires Channel .. 66 OOB (Tunneled SMBus) Message Channel .. 82 Run-time Flash Access Channel .. 85 Slave Buffer Management .. 89 Transact io n Orde r ing R u 91 Zero Length Read and Write .. 92 6 Link Layer .. 93 Single I/O, Dual I/O and Quad I/O Modes .. 93 4 327432-004 Cyclic Redundancy Check (CRC).. 97 7 Slave Registers .. 99 Status Register .. 99 C apabilit ies and C o nfig urat io n Reg isters .. 100 8 Operat ing Spec if icat io 111 E lectr ica l S pecif icat io n .. 111 Tim ing 112 9 System Architecture.

8 115 Interrupts .. 115 Error Detection and Handling .. 115 Slave s Detected Errors .. 116 Master s Detected Errors .. 124 127 eSPI Reset# .. 127 In-band RESET Command .. 128 Power Management Event (PME) .. 129 Pow er Sequenc ing & In it ia liz atio 129 Exit fro m 129 Figures Figure 1: EC/BMC/SIO Communicat ion over LPC .. 10 Figure 2: EC/BMC/SIO Communicat ion over 11 Fig ure 3: Examp le o f LPC b us a nd A dd it io na l eSP I b us be h in d the eSP I .. 12 Fig ure 4: Single Master-Single Slave with eSPI Reset# from Slave to 14 Figure 5: Single Master-Single Slave with eSPI Reset# from Master to 15 Figure 6: Single Master-Mu lt ip le S laves w it h Tw o eSPI Reset#.

9 16 Figure 7: Single Master-S ing le S lave (Mu lt ip le C ha nne ls) .. 18 Figure 8: Single Master-Mu lt ip le S laves .. 20 Figure 9: EC/BMC/SIO Communicat ion Over eSPI Channels .. 21 Figure 10: Basic eSPI Protocol .. 24 Fig ure 11: S lave Tr igge red T ransact io n (S in g le Master-S lave) .. 25 Figure 12: Slave Triggered Transact io n (Mu lt ip le S lave) .. 27 Figure 13: Command Opcode .. 28 Figure 14: Turn-Aro un d T ime (T AR = 2 clo ck).. 33 Figure 15: Response Field .. 34 Figure 16: Slave s Status Register Definition .. 36 Fig ure 17: Flo w Dia gram fo r a S lave to Master Periphe ra l Po sted Wr ite .. 40 Fig ure 18: Flo w Dia gram fo r a Back-to-back Slave to Master Peripheral Posted Write 40 327432-004 5 Figure 19: Flow Diagram for a Slave to Master Peripheral Posted Write passes Non-posted.

10 41 Figure 20: GET_STATUS 42 Figure 21: GET_STATUS Command (with Response Modif ier) .. 43 Figure 22: GET_CONFIGURATION 43 Figure 23: SET_CONFIGURATION Command .. 44 Figure 24: Connected Master Initiated Non-Posted Transaction .. 45 Figure 25: Deferred Master Initiated Non-Posted Transaction .. 46 Fig ure 26: Master In it iated Sho rt No n-Posted Transaction .. 47 Fig ure 27: S lave In it iated No n-Posted Transaction .. 48 Fig ure 28: Master In it iated Po sted Transact io 49 Figure 29: Master Initiated Short Posted Transaction .. 49 Fig ure 30: S lave In it iated Po sted Tra nsactio n .. 50 Fig ure 31: Pipe line d Back-to-Back Bus Mastering Posted Write 51 Fig ure 32: Master In it iated No n-Posted Transaction Responded w ith WAIT STATE.