Transcription of Intel Stratix 10
1 Intel Stratix 1 0 Intel Stratix 10 Mx (DraM SySteM-In-Package) ProDuct tableNotes:1. LE counts valid in comparing across Altera devices, and are conservative vs. competing Fixed point performance assumes the use of Floating-point performance is IEEE-754 compliant Quad-core ARM Cortex-A53 hard processor system not available in Stratix 10 MX A subset of pins for each package are used for high-voltage V and V All data is preliminary and subject to change without prior LINEMX 1650MX 1650MX 1650MX 2100MX 2100MX 2100MX 2100 ResourcesLogic elements (LEs)11,679,0001,679,0001,679,0002,073,0 002,073,0002,073,0002,073,000 Adaptive logic modules (ALMs)569,200569,200569,200702,720702,72 0702,720702,720 ALM registers2,276,8002,276,8002,276,8002,81 0,8802,810,8802,810,8802,810,880 Hyper-Registers from Intel HyperflexTM FPGA architectureMillions of Hyper-Registers distributed throughout the monolithic FPGA fabricProgrammable clock trees synthesizableHundreds of synthesizable clock treesHBM2 high-bandwidth DRAM memory (GBytes)816888168eSRAM memory blocks2222222eSRAM memory size (Mb)
2 Memory blocks6,1626,1626,1626,8476,8476,8476,84 7M20K memory size (Mb)120120120134134134134 MLAB memory size (Mb)99911111111 Variable-precision digital signal processing (DSP) blocks3,3263,3263,3263,9603,9603,9603,96 018 x 19 multipliers6,6526,6526,6527,9207,9207,92 07,920 Peak fixed-point performance (TMACS) floating-point performance (TFLOPS) and Architectural FeaturesSecure device managerAES-256/SHA-256 bitsream encryption/authentication, physically unclonable function (PUF), ECDSA 256/384 boot code authentication, side channel attack protectionHard processor system4 Maximum user I/O pins656656584640656656584 LVDS pairs Gbps (RX or TX)312312288312312312288 Total full duplex transceiver count96969648969696 GXE transceiver count - PAM4 (up to Gbps) or NRZ (up to Gbps)0036 PAM-472 NRZ00036 PAM-472 NRZGXT transceiver count - NRZ (up to Gbps)64641632646416GX transceiver count - NRZ (up to Gbps)323281632328 PCI Express* (PCIe*) hard intellectual property (IP) blocks (Gen3 x16)4412441100G Ethernet MAC (no FEC) hard IP blocks4412441100G Ethernet MAC + FEC hard IP blocks001200012 Memory devices supportedDDR4, DDR3, DDR2, DDR, QDR II, QDR II+, RLDRAM II, RLDRAM 3, HMC, MoSysPackage Options and I/O Pins: General-Purpose I/O (GPIO) Count, High-Voltage I/O Count, LVDS Pairs, E-Tile Transceiver Count and H-Tile Transceiver Count5, 6F2597 pin ( mm x mm, pitch)656, 32, 312, 0, 96656, 32, 312, 0, 96 640, 16, 312, 0, 48656, 32, 312, 0, 96656, 32, 312, 0, 96 F2912 pin (55 mm x 55 mm, mm pitch) 584, 8, 288, 72, 24 584, 8, 288, 72, 24656,32,312,0,96 Numbers indicate total GPIO count, high-voltage I/O count, LVDS pairs, E-Tile transceiver count and H-Tile transceiver pin migration path.
3 Intel Corporation. Intel , the Intel logo, the Intel Inside mark and logo, the Intel . Experience What s Inside mark and logo, Altera, Arria, Cyclone, Enpirion, Intel Atom, Intel Core, Intel Xeon, MAX, Nios, Quartus and Stratix are trademarks of Intel Corporation or its subsidiaries in the and/or other countries. See Trademarks on for full list of Intel trademarks. *Other marks and brands may be claimed as the property of e n
