OSCI-SystemC 合成サブセット Draft1.3 1 章 抄訳

1 Copyright 2010 JEITA, All rights reserved 1 OSCI-SystemC 1 2010 5 JEITA EDA SystemC Working Group Copyright 2010 JEITA, All rights reserved 2 SystemC synthesizable Subset draft 1 OSCI SystemC synthesizable Subset draft 1 2 OSCI SystemC synthesizable Subset draft Open SystemC Initiative(OSCI) Synthesis Working Group (SWG) synthesizable -SystemC (SSC) SystemC SystemC EDA SSC C++ IEEE1666 SystemC SWG SystemC SystemC OSCI SystemC SystemC synthesizable -SystemC(SSC)

2 1 SystemC SCC SystemC SCC SystemC SystemC RT synthesizable -SystemC SystemC RTL Copyright 2010 JEITA, All rights reserved 3 Synthesis SystemC "shall" ( ) "shall" ( ) "required to" ( ) "should" ( ) "should" "recomended" ( ) "may" ) "may" "permitted" ( ) " " SystemC (Legal) " " SystemC " " Copyright 2010 JEITA, All rights reserved 4 Supported: ( ) " " Extended: ( ) " " C++ Ignored.

3 ( ) " " " " "Ignored" Not Supported : ( ) a) SystemC C++ ( sensitive) b) SystemC c) d) e) f) - - g) ::= ( ) h) (|) 2 (,) i) [ ] 1 Copyright 2010 JEITA, All rights reserved 5 2 init-declarator ::= declarator [ initializer ] init-declarator.

4 = declarator | declarator initializer j) NOTE k) SystemC (TLM) (RTL) HW/SW HW (TLM) HW(RTL) SW( ) SW( ) HW SW Copyright 2010 JEITA, All rights reserved 6 YA P I1.

5 ( C/C++/Matlab ) HW/SW FIFO Kahn (KPN) KPN KPN ( IP) Kahn YAPI YAPI YAPI SystemC SystemC YAPI 1 YAPI(Y-chart API) Kahn Process Network C++ Philips Research Copyright 2010 JEITA, All rights reserved 7 SystemC YAPI KPN (TLM) (SoC) OSCI TLM OSCI TLM WG TLM (computation)

6 (communication) OSCI TLM WG 1. Un-Timed (UT): FIFO 2. Loosely Timed (LT): OS LT 3. Approximately Timed (AT): 4. Cycle Accurate (CA): RTL 1 1 UT LT sc_time(10,SC_NS) AT CA / IO (RTL)

7 RTL Verilog/VHDL SystemVerilog HDL GDSII SystemC Copyright 2010 JEITA, All rights reserved 8 RTL RTL z a*b word z z FSM (FSM) if-then-else case z ( ) explicit-state machine explicit-state machine RTL ( ) enable (retiming) RTL RTL IEEE Standard 1076-2004 VHDL SystemC RTL IO IO : 1 RTL ( ) continue exit (if-then-else case ) wait RTL / ( ) ( RTL ) Y=P(X) P X={x1, x2.}

8 , xn, v1, v2, .., vm} xi, 1 i n vj, 1 j m Y = {y1, y2, .., yl} . : SC_MODULE( AddMul_1 ) { sc_in< sc_clock > clk; sc_in< sc_uint<16> > a, b, c; sc_out< sc_uint<32> > result; void addmul_1() { result = a + (b * c); } SC_CTOR( AddMul_1 ) { Copyright 2010 JEITA, All rights reserved 9 SC_METHOD( addmul_1 ); sensitive << (); } }; P void addmul_1(); X = {x1, v1, v2, v3} x1 = clk, v1 = a, v2 = b and v3 = c; Y = {y1} y1 = result [De Micheli 94 Knapp 96] Y = P(X) X Y X xi P Y UT X X xi P X Y . : SC_MODULE( AddMul_2 ) { sc_in< sc_uint<16> > a, b, c; sc_out< sc_uint<32> > result; void addmul_2() { result = a + (b * c); } SC_CTOR( AddMul_2 ) { SC_METHOD( addmul_2 ); sensitive << a << b << c; } }; P addmul_2 (); X = {x1, x2, x3 },x1 = a, x2 = b, x3 = c; Y = {y1}, y1 = result.

9 : SC_MODULE( AddMul_3 ) { sc_in< sc_clock > clk; sc_in< bool > rst; sc_in< sc_uint<16> > a, b, c; sc_out< sc_uint<32> > result; void addmul_3() { result = 0; wait(); while (1) { result = a + (b * c); Copyright 2010 JEITA, All rights reserved 10 wait(); } } SC_CTOR( AddMul_3 ) { SC_CTHREAD( addmul_3, () ); reset_signal_is(rst, false); } }; P void addmul_3() SC_CTHREAD reset_signal_is () clk rst clk rst X = {x1, 2, v1, v2, v3} x1 = clk x2 = rst v1 = a v2 = b v3 = c Y = {y1} y1 = result SC_CTHREAD reset_signal_is() (RTL) / RTL RTL : 1.

10 2. Y = P(X) Y P P and or Y 3. RTL (FSM ) FSM FSM FSM with Datapath(FSMD) FSM datapath . Example: SC_MODULE( AddMul_4 ) { sc_in< sc_clock > clk; sc_in< bool > rst; sc_in< sc_uint<16> > a, b, c; sc_out< sc_uint<32> > result; void addmul_4() { sc_signal<sc_uint<32> > tmp1; Copyright 2010 JEITA, All rights reserved 11 tmp1 = 0; result = 0; wait(); while (1) { tmp1 = b * c; wait(); result = a + tmp1; wait(); } } SC_CTOR( AddMul_4 ) { SC_CTHREAD( addmul_4, () ); reset_signal_is(rst, false); } }; P = void addmul_4 () if(rst==false){} FSMD while(l){} - tmpl SC_CTHREAD reset_signal_is() wait() SC_CTHREAD() AND OR NOT XOR.