256 10 FPGA IP User Guide - intel.com

1 external memory Interfaces intel Stratix 10 FPGA IP User GuideUpdated for intel Quartus Prime design Suite: FeedbackUG-S10 EMI | document on the web: PDF | HTMLC ontents1. external memory Interfaces intel Stratix 10 FPGA IP intel Stratix 10 EMIF IP design intel Stratix 10 EMIF IP design intel Stratix 10 EMIF IP Product intel Stratix 10 EMIF Architecture: intel Stratix 10 EMIF Architecture: I/O intel Stratix 10 EMIF Architecture: I/O intel Stratix 10 EMIF Architecture: I/O intel Stratix 10 EMIF Architecture: I/O intel Stratix 10 EMIF Architecture: I/O intel Stratix 10 EMIF Architecture: Input DQS Clock intel Stratix 10 EMIF Architecture: PHY Clock intel Stratix 10 EMIF Architecture: PLL Reference Clock intel Stratix 10 EMIF Architecture: Clock Phase intel Stratix 10 EMIF intel Stratix 10 EMIF DQS intel Stratix 10 EMIF intel Stratix 10 Calibration Stages .. intel Stratix 10 Calibration Stages intel Stratix 10 Calibration intel Stratix 10 Calibration intel Stratix 10 EMIF IP Hard memory intel Stratix 10 Hard memory Controller Rate Conversion Hardware Resource Sharing Among Multiple intel Stratix 10 I/O SSM I/O Bank PLL Reference Clock Core Clock Network User-requested Reset in intel Stratix 10 EMIF intel Stratix 10 EMIF for Hard Processor Restrictions on I/O Bank Usage for intel Stratix 10 EMIF IP with Using the EMIF Debug Toolkit with intel Stratix 10 HPS intel Stratix 10 EMIF Ping Pong intel Stratix 10 Ping Pong PHY Feature intel Stratix 10 Ping Pong PHY intel Stratix 10 Ping Pong PHY intel Stratix 10 Ping Pong PHY Using the Ping Pong Ping Pong PHY Simulation Example 483.

2 intel Stratix 10 EMIF IP End-User interface and Signal intel Stratix 10 EMIF IP Interfaces for intel Stratix 10 EMIF IP Interfaces for intel Stratix 10 EMIF IP Interfaces for QDR II/II+/II+ intel Stratix 10 EMIF IP Interfaces for memory Interfaces intel Stratix 10 FPGA IP User GuideSend intel Stratix 10 EMIF IP Interfaces for RLDRAM AFI AFI Clock and Reset AFI Address and Command AFI Write Data AFI Read Data AFI Calibration Status AFI Tracking Management AFI Shadow Register Management AFI Timing AFI Address and Command Timing AFI Write Sequence Timing AFI Read Sequence Timing AFI Calibration Status Timing intel Stratix 10 memory Mapped Register (MMR) ecc3: ECC Error and Interrupt ecc4: Status and Error ecc5: Address of Most Recent ecc6: Address of Most Recent Correction Command ecc7: Extension for Address of Most Recent ecc8: Extension for Address of Most Recent Correction Command FeedbackExternal memory Interfaces intel Stratix 10 FPGA IP User Guide34.

3 intel Stratix 10 EMIF Simulating memory Simulation Simulation Calibration Abstract PHY Simulation Functional Simulation with Verilog Functional Simulation with Simulating the design intel Stratix 10 EMIF IP for Parameter intel Stratix 10 EMIF IP DDR3 Parameters: intel Stratix 10 EMIF IP DDR3 Parameters: FPGA intel Stratix 10 EMIF IP DDR3 Parameters: intel Stratix 10 EMIF IP DDR3 Parameters: Mem intel Stratix 10 EMIF IP DDR3 Parameters: Mem intel Stratix 10 EMIF IP DDR3 Parameters: intel Stratix 10 EMIF IP DDR3 Parameters: intel Stratix 10 EMIF IP DDR3 Parameters: intel Stratix 10 EMIF IP DDR3 Parameters: Example Board Skew Equations for DDR3 Board Skew Pin and Resource interface FPGA Pin Guidelines for intel Stratix 10 EMIF DDR3 Board design Terminations for DDR3 and DDR4 with intel Stratix 10 Channel Signal Integrity Layout design Layout Package 1856. intel Stratix 10 EMIF IP for Parameter intel Stratix 10 EMIF IP DDR4 Parameters: intel Stratix 10 EMIF IP DDR4 Parameters: FPGA intel Stratix 10 EMIF IP DDR4 Parameters: intel Stratix 10 EMIF IP DDR4 Parameters: Mem intel Stratix 10 EMIF IP DDR4 Parameters: Mem intel Stratix 10 EMIF IP DDR4 Parameters: intel Stratix 10 EMIF IP DDR4 Parameters: intel Stratix 10 EMIF IP DDR4 Parameters: intel Stratix 10 EMIF IP DDR4 Parameters: Example Board Skew Equations for DDR4 Board Skew Pin and Resource interface FPGA Pin Guidelines for intel Stratix 10 EMIF memory Interfaces intel Stratix 10 FPGA IP User GuideSend Resource Sharing Guidelines (Multiple Interfaces).

4 DDR4 Board design Terminations for DDR3 and DDR4 with intel Stratix 10 Channel Signal Integrity Layout design Layout Package 2437. intel Stratix 10 EMIF IP for QDR II/II+/II+ Parameter intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: FPGA intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Mem intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Board Skew Equations for QDRII, QDRII+, and QDRII+ Xtreme Board Skew Pin and Resource interface QDR II/II+/II+ Xtreme Board design QDR II SRAM General Layout QDR II Layout QDR II SRAM Layout Package 2758. intel Stratix 10 EMIF IP for Parameter intel Stratix 10 EMIF IP QDR-IV Parameters: intel Stratix 10 EMIF IP QDR-IV Parameters: FPGA intel Stratix 10 EMIF IP QDR-IV Parameters: intel Stratix 10 EMIF IP QDR-IV Parameters: Mem intel Stratix 10 EMIF IP QDR-IV Parameters: intel Stratix 10 EMIF IP QDR-IV Parameters: intel Stratix 10 EMIF IP QDR-IV Parameters: intel Stratix 10 EMIF IP QDR-IV Parameters: Example Board Skew Equations for QDR-IV Board Skew Pin and Resource interface QDR-IV Board design QDR-IV Layout General Layout QDR-IV Layout Package 3039.

5 intel Stratix 10 EMIF IP for RLDRAM Parameter FeedbackExternal memory Interfaces intel Stratix 10 FPGA IP User intel Stratix 10 EMIF IP RLDRAM 3 Parameters: intel Stratix 10 EMIF IP RLDRAM 3 Parameters: FPGA intel Stratix 10 EMIF IP RLDRAM 3 Parameters: intel Stratix 10 EMIF IP RLDRAM 3 Parameters: Mem intel Stratix 10 EMIF IP RLDRAM 3 Parameters: intel Stratix 10 EMIF IP RLDRAM 3 Parameters: intel Stratix 10 EMIF IP RLDRAM 3 Parameters: intel Stratix 10 EMIF IP RLDRAM 3 Parameters: Example Board Skew Equations for RLDRAM 3 Board Skew Pin and Resource interface RLDRAM 3 Board design RLDRAM 3 General Layout RLDRAM 3 Layout Layout Package 33410. intel Stratix 10 EMIF IP Timing Timing Closure .. Timing Timing Report Optimizing Early I/O Timing Performing Early I/O Timing 34411. Optimizing Controller interface Bank Management Data Improving Controller Auto-Precharge Bank Additive Latency and Bank User-Controlled Frequency of Series of Reads or Data Starvation Command Enable Command Priority intel Stratix 10 EMIF IP interface Configuration Performance interface Configuration Bottleneck and Efficiency Functional Issue intel IP memory Vendor memory memory Interfaces intel Stratix 10 FPGA IP User GuideSend Transcript Window Modifying the Example Driver to Replicate the Timing Issue Evaluating FPGA Timing Evaluating external memory interface Timing Verifying memory IP Using the Signal Tap II Logic Signals to Monitor with the Signal Tap II Logic Hardware Debugging Create a Simplified design that Demonstrates the Same Measure Power Distribution Measure Signal Integrity and Setup and Hold Vary Operate at a Lower Determine Whether the Issue Exists in

6 Previous Versions of Determine Whether the Issue Exists in the Current Version of Try A Different Try Other Debugging Categorizing Hardware Signal Integrity Hardware and Calibration Debugging intel Stratix 10 EMIF external memory interface Debug On-Chip Debug for intel Stratix Configuring Your EMIF IP for Use with the Debug Example Tcl Script for Running the EMIF Debug Using the EMIF Debug Toolkit with intel Stratix 10 HPS intel Stratix 10 EMIF Debugging User Setup and On-Chip Debug Port for intel Stratix 10 EMIF EMIF On-Chip Debug Access On-Die Termination Calibration .. Eye Diagram .. Driver Margining for intel Stratix 10 EMIF Determining Efficiency Monitor and Protocol Including the Efficiency Monitor and Protocol Checker in Your Generated IP Running the Efficiency Monitor with the external memory Debug Communicating Directly to the Efficiency Monitor and Protocol Calibration Adjustment Delay Step Sizes for intel Stratix 10 Output and Strobe Enable Minimum and Maximum Phase 40413.

7 Document Revision History for external memory Interfaces intel Stratix 10 FPGAIP User 405 ContentsSend FeedbackExternal memory Interfaces intel Stratix 10 FPGA IP User Guide71. external memory Interfaces intel Stratix 10 FPGA IPIntroductionIntel's fast, efficient, and low-latency external memory interface (EMIF) intellectualproperty (IP) cores easily interface with today's higher speed memory can easily implement the EMIF IP core functions through the intel Quartus Prime software. The intel Quartus Prime software also provides external memorytoolkits that help you test the implementation of the IP in the external memory Interfaces intel Stratix 10 FPGA IP (referred to hereafter as theIntel Stratix 10 EMIF IP) provides the following components: A physical layer interface (PHY) which builds the data path and manages timingtransfers between the FPGA and the memory device. A memory controller which implements all the memory commands and protocol-level information on the maximum speeds supported by the external memory interfaceIP, refer to the external memory interface Spec Stratix 10 EMIF IP Protocol and Feature Support Supports DDR4, DDR3, and DDR3L protocols with hard memory controller andhard PHY.

8 Supports QDR-IV, QDR II + Xtreme, QDR II +, and QDR II using soft memorycontroller and hard PHY. Supports RLDRAM 3 using third-party soft controller. Supports UDIMM, RDIMM, LRDIMM and SODIMM memory devices. Supports 3D Stacked Die for DDR4 devices. Supports up to 4 physical ranks. Supports Ping Pong PHY mode, allowing two memory controllers to sharecommand, address, and control pins. Supports error correction code (ECC) for both hard memory controller and softmemory Information intel FPGA IP for external memory Interfaces - Support Center intel Stratix 10 General Purpose I/O User GuideUG-S10 EMI | FeedbackIntel Corporation. All rights reserved. intel , the intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartusand Stratix words and logos are trademarks of intel Corporation or its subsidiaries in the and/or othercountries. intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with intel 's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice.

9 intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by intel . Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of intel Stratix 10 EMIF IP design FlowIntel recommends creating an example top-level file with the desired pin outs and allinterface IPs instantiated. This enables the intel Quartus Prime software to validatethe design and resource allocation before PCB and schematic sign following figure shows the design flow to provide the fastest out-of-the-boxexperience with the EMIF IP design FlowSelect a memory Device and FPGAPlan Pin/FPGA Resource UsageInitiate Board LayoutParameterize and Generate EMIF IPCompile design and Verify TimingVerify Functionality on BoardDetermine memory RequirementsPerform Board SimulationUpdate Board ParametersVerify IP ParametersDesign CompletedDebugIs Timing Passing?

10 Is design Working?Perform Functional SimulationYesNoNoYesRelated Information Introduction to intel FPGA IP Cores Generating a Combined Simulator Setup Script Project Management Best Practices1. external memory Interfaces intel Stratix 10 FPGA IP IntroductionUG-S10 EMI | FeedbackExternal memory Interfaces intel Stratix 10 FPGA IP User intel Stratix 10 EMIF IP design ChecklistRefer to the following checklist as a quick reference for information about each step inthe EMIF design design ChecklistDesign StepDescriptionResourcesSelect an FPGANot all intel FPGAs support all memory typesand configurations. To help with the FPGA selection process, refer to these resources. intel FPGA Product Selector external memory interface DeviceSelector external memory interface SpecEstimatorParameterize the IPCorrect IP parameterization is important forgood EMIF IP operation. These resources definethe memory parameters during IP generation. DDR3 Parameter Descriptions DDR4 Parameter Descriptions QDR II/II+/II+ Xtreme ParameterDescriptions QDR-IV Parameter Descriptions RLDRAM 3 Parameter DescriptionsGenerate initial IP andexample designAfter you have parameterized the EMIF IP, youcan generate the IP, along with an optionalexample design .